"John" == John Woodgate <jmw@...> writes:

I am trying to save the BOM as a .CSV file into the folder with the
other KiCad files, but it doesn't save. Wherever I try to save it
to, I get a message box that says 'Do you want to use a path
relative to C:\----------filter KiCad\?' and whether I answer YES,
or NO and enter a different file location, the file seems not to be
saved anywhere. Please advise.

What version of Kicad are you using? And what about just saving to
C:\temp and then moving it over to the project folder?

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I am trying to save the BOM as a .CSV file into the folder with the other KiCad files, but it doesn't save. Wherever I try to save it to, I get a message box that says 'Do you want to use a path relative to C:\----------filter KiCad\?' and whether I answer YES, or NO and enter a different file location, the file seems not to be saved anywhere. Please advise.

OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying

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In the case of the 200p + 18p, it would be hard to avoid COG/NP0 ceramic anyway, so the temperature effects are probably not much of a consideration.

I'm not saying there is no advantage in making both caps 1%, just that if the 2 values in parallel differ by a factor of ten, the for the same influence on the overall tolerance, the small cap can have a tolerance 10x as large. Clearly 10% will never be as tight as 1%.

--

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It's completely true, but, as you say, it's not the whole, very exhausting, story. I am commenting at the very basic level of 'What about tolerance?' Your input is at a second level of concern. I could add that it's not necessarily a good idea to use a wide-tolerance component, because the wide tolerance is needed because the dielectric has large temperature and voltage coefficients of capacitance. But to keep things simple, I won't add that. (;-) However, your assertion about 200 pF +/- 1% and18 pF +/- 10% is not quite true, I think: it gives extreme values of 221.8 and 214.2, whereas 218 +/- 1% gives 220.18 and 215.82.

On 27/10/2024 11:20, John Woodgate wrote:

It's not clear what you are doing about component tolerances. You can get 218 pF with a 150 pF and a 68 pF in parallel. That is just within +1% of 216 pF. A single 220 pF is within +2%. If all your four capacitors have +/-1% tolerance, your 216 pF will also have +/-1% tolerance, but there are many additional stray capacitances with this arrangement. Fewer capacitors, fewer strays and simpler construction.

What you're saying about tolerance is only half-true. Paralleling multiple capacitances doesn't change the worst cases. But it does change the standard deviation. Assuming 4 equal valued capacitors in parallel reduces σ by √4. If the nominal values of the capacitors are not equal the situation is much more complicated.

In general, it is a much better idea, when trying to obtain a non-standard value, to get as close as you can with one high tolerance capacitor and add a much smaller one in parallel that can be a much looser tolerance. You can get 218p with 200p and 18p. You only need to specify the 200p as a 1%. The 18p could be a 10% for the same effect on overall tolerance.

--
Regards,
Tony

-- 
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying

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It's not clear what you are doing about component tolerances. You can get 218 pF with a 150 pF and a 68 pF in parallel. That is just within +1% of 216 pF. A single 220 pF is within +2%. If all your four capacitors have +/-1% tolerance, your 216 pF will also have +/-1% tolerance, but there are many additional stray capacitances with this arrangement. Fewer capacitors, fewer strays and simpler construction.

What you're saying about tolerance is only half-true. Paralleling multiple capacitances doesn't change the worst cases. But it does change the standard deviation. Assuming 4 equal valued capacitors in parallel reduces σ by √4. If the nominal values of the capacitors are not equal the situation is much more complicated.

In general, it is a much better idea, when trying to obtain a non-standard value, to get as close as you can with one high tolerance capacitor and add a much smaller one in parallel that can be a much looser tolerance. You can get 218p with 200p and 18p. You only need to specify the 200p as a 1%. The 18p could be a 10% for the same effect on overall tolerance.

--
Regards,
Tony

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It's not clear what you are doing about component tolerances. You can get 218 pF with a 150 pF and a 68 pF in parallel. That is just within +1% of 216 pF. A single 220 pF is within +2%. If all your four capacitors have +/-1% tolerance, your 216 pF will also have +/-1% tolerance, but there are many additional stray capacitances with this arrangement. Fewer capacitors, fewer strays and simpler construction.

Hi all,

?

Many thanks for your efforts to fix my dilemma.

?

I've come up with a work-around that is reasonable painless and makes it easy for the next project builder to see what I've done.

?

So basically it works like this:

I've added global labels to each composite capacitance and hidden the reference ID. (refer the following image)? The footprint has also been removed so there is nothing to place on the PCB. (so far; DRC tests have not yet been run)

?

?

Then I've created the composite capacitors on a separate sheet so that it doesn't clutter the main schematic.

Each of these capacitors has it's own separate footprint which gets placed onto the PCB as per normal.? (It seems impossible to have a many-to-one capacitor to footprint relationship).

Whilst the cap on the main schematic does still appear in the BOM, it's component caps are listed correctly and it should be easy enough to figure out what is going on.

?

I haven't extensively tested this yet, but so for the ERC is not throwing any errors or warnings.

?

I think this is an acceptable compromise.

Again, thanks for all you input ... it has been helpful.

?

Cheers

Luke

?

-- 
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying

To achieve what you want, I just use 4 footprints. No problem for BOM. But in PCB, I just hide all the value text. Then add a field at one of them says "4x100nF". Just like that.?

When I need to stack surface-mount components I use a bit of "blue painters tape" on my bench with the sticky side up. I place a few large washers or similar on the ends of the tape to keep it from sliding around or curling.

Then, just stick the parts to the tape in the proper alignment and solder them together. I've even built an "order 7" elliptic filter that way. :-)

Steve

The easiest way is to manually enter that into the bom and put instructions in the assembly drawing. It will probably cause pick and place issue (and it would not show up correctly as well), so it would be limited to being hand placed and soldered.

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On 10/10/2024 06:00, Varuzhan Danielyan wrote:

I use W10 on one PC and W11 on the other.

?

The "Pin properties" is Ok, the problem is only with the "Pin table".

Try this:

1. With the Pin Table visible, right-click anywhere on the column header row.
2. You should get a checklist of columns to make visible.
3. There are 14 available columns - some are not enabled by default.
4. Enable "Length".

You should now be fixed.

Like this:

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I checked on my installation, but the PinTable is missing the Y-Position column (see attached image) :-)
Something is wrong....

KiCad v8.0.5, release build on Windows 10

Regards,

Peter

Please see message? #25275

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I use W10 on one PC and W11 on the other.

?

The "Pin properties" is Ok, the problem is only with the "Pin table".

Try this:

1. With the Pin Table visible, right-click anywhere on the column header row.
2. You should get a checklist of columns to make visible.
3. There are 14 available columns - some are not enabled by default.
4. Enable "Length".

You should now be fixed.

--
Regards,
Tony