It's not clear what you are doing about
component tolerances. You can get 218 pF with a 150 pF and a 68
pF in parallel. That is just within +1% of 216 pF. A single 220
pF is within +2%. If all your four capacitors have +/-1%
tolerance, your 216 pF will also have +/-1% tolerance, but there
are many additional stray capacitances with this arrangement.
Fewer capacitors, fewer strays and simpler construction.
On 2024-10-27 10:08, Luke Vogel wrote:
Hi all,
?
Many thanks for your efforts to fix my dilemma.
?
I've come up with a work-around that is reasonable painless
and makes it easy for the next project builder to see what I've
done.
?
So basically it works like this:
I've added global labels to each composite capacitance and
hidden the reference ID. (refer the following image)? The
footprint has also been removed so there is nothing to place on
the PCB. (so far; DRC tests have not yet been run)
?
?
Then
I've created the composite capacitors on a separate sheet so
that it doesn't clutter the main schematic.
Each
of these capacitors has it's own separate footprint which gets
placed onto the PCB as per normal.? (It seems impossible to
have a many-to-one capacitor to footprint relationship).
Whilst
the cap on the main schematic does still appear in the BOM,
it's component caps are listed correctly and it should be easy
enough to figure out what is going on.
?
I
haven't extensively tested this yet, but so for the ERC is not
throwing any errors or warnings.
?
I
think this is an acceptable compromise.
Again, thanks for all you input ... it has been helpful.
?
Cheers
Luke
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--
OOO - Own Opinions Only
Best Wishes
John Woodgate
Keep trying
John Woodgate