Hi all,
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Many thanks for your efforts to fix my dilemma.
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I've come up with a work-around that is reasonable painless and makes it easy for the next project builder to see what I've done.
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So basically it works like this:
I've added global labels to each composite capacitance and hidden the reference ID. (refer the following image)? The footprint has also been removed so there is nothing to place on the PCB. (so far; DRC tests have not yet been run)
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Then I've created the composite capacitors on a separate sheet so that it doesn't clutter the main schematic.
Each of these capacitors has it's own separate footprint which gets placed onto the PCB as per normal.? (It seems impossible to have a many-to-one capacitor to footprint relationship).
Whilst the cap on the main schematic does still appear in the BOM, it's component caps are listed correctly and it should be easy enough to figure out what is going on.
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I haven't extensively tested this yet, but so for the ERC is not throwing any errors or warnings.
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I think this is an acceptable compromise.
Again, thanks for all you input ... it has been helpful.
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Cheers
Luke
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Luke Vogel