Re: 468 DSO Calibration/troubleshooting
Hi Fabio,
Firstly, thank you for giving this some thought. Some of my observations:
1. Check STORAGE WINDOW Operation. This all works fine, except that when going to "d. set STORAGE WINDOW PRE TRIG" the triggering jitter becomes quite noticeable; it is less so in POST TRIG.
2. Check A and B+ GATES.
Set NON-STORE On; A TIME/DIV 0.1 ms; B TIME/DIV 20 us. All works as expected, except for the jitter when in NORM storage mode - Non-storage there is a rock-solid trace with no jitter at all.
3. Check/Adjust Storage NORM Trigger DC Balance (R126)
Set CH1 VOLTS/DIV 5mV; HORIZ DISPLAY A. Remember that the A sweep is still at 0.1 ms/DIV and so there are some 50 full cycles of a 50-kHz sine-wave. Trying to set anything with the A TRIGGER LEVEL is nigh on impossible. I think the sweep should be A at 20 us/DIV, showing ten full cycles. The problem now is that trying to align the leading edge with the second vertical graticule line at the horizontal centre graticule line results in loss of triggering. This alignment can be done using the horizontal position control, however. When aligned in this way, switching between AC and DC Trigger coupling of the A sweep shows no movement.
Have I achieved what is required, or am I again missing something?
It is a pity that Reed Dickinson hasn't seen this thread, as I think he is a bit of an expert on the 468 and he certainly holds them in some respect. However, I repeat my thanks to you, Fabio.
Regards, Colin.
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-----Original Message----- From: [email protected] [mailto: [email protected]] On Behalf Of Fabio Trevisan Sent: 05 July 2018 17:09 To: [email protected]Subject: Re: [TekScopes] 468 DSO Calibration/troubleshooting Hello Collin, Regarding my last statement (the P.S.), that this check should be made in "non-store" mode, I'm giving second thoughts at it. I`m not sure yet, but I just found out that there are two "NORM triggering DC balance" adjustments... one on the analog side and another one on the storage side... So, it seems weird that we could even be able to adjust the STORAGE NORM triggering DC balance in any mode that isn't a storage mode. On the other hand, I may still be correct on my initial assumption, because the flow of the instructions and the explicit instruction to set "NON STORE" to ON, at Section #2, step g. I`m only not sure if that adjustment (R126) would be even doable while in NON STORE mode... I`ll get back to it as soon as I can dig a little bit more on the manual. Rgrds, Fabio On Thu, Jul 5, 2018 at 08:23 am, Fabio Trevisan wrote:
Hello Colin,
I don't own a 468 and have no particular experience with it, but I have the
manuals (in PDF form) and since your doubt is related to understaing of the
instructions, I decided to give it a try and see if I could make sense out of
this part of the instruction that you're doubtful at.
At this step, the only thing that doesn't seem really clear to me is why it
asks specifically to align the leading edge of the sine-wave to the 2nd
graticule line (why the 2nd.???)..
But, regardless of not understanding that, I think the purpose of this
calibration step is clear... Is to make a "differential" assessment of the
triggering level shift, between using AC triggering coupling and DC triggering
coupling...
So, basically what it is asking for, is for you to make sure that the
triggering point doesn't move between AC and DC coupling, when you're actually
feeding a signal that already swings about 0V...
I mean, if the input signal is swinging about 0V (i.e. if it doesn't contain a
DC level), changing the triggering coupling from AC to DC should not make any
difference, and therefore, the triggering point, whatever it was set to before
switching to DC, the wave form must remain in the same position.
If the waveform shifts horizontally, than it means that the triggering point
"seen" by the triggering circuit have changed when switching over from AC to
DC, which it shouldn't.
Giving second thoughts to the instruction, it's not much different than
adjusting the Norm DC triggering balance of a 464 (which I own), and probably
the same as the 465 (more common).
the only difference is that, for the 464, we're asked for looking at the very
beginning of the sweep, and not at the 2nd vertical graticule line (i.e. 1
division after the sweep actually started).
This difference in procedure (from the non store scope), doesn't actually
matter to what the DC balance adjustment is doing (which is nothing more than
shifting the DC level of the actual signal being fed to the triggering input
buffer, with the intent to making it match with the level of the same signal
when AC coupled).
The only reason I think they're doing that (adjusting at the 2nd vertical
graticule line iso at the beginning of the sweep), is because this point is
about the actual point on the display where the triggering point of the
digital stored signal is supposed to be displayed.
P.S. Also note that, although this adjustment step is called "Check / Adjust
STORAGE NORM Trigger DC balance", by following the instructions coming from
the previous steps, I understand (it's my conclusion though) that this
adjustment is not meant to be performed in storage mode.
The previous section, "#2 Check A and B+ gates", at step g. it asks you to
set the "NON STORE" button to ON position... and then it doesn't ever ask you
to change it to OFF, so, by the flow of the procedure, the #3 check is to be
performed in NON STORE mode.
Therefore, this jitter that you mentioned you're getting on storage mode
should not interfere with you performing this adjustment (because it's done in
NON STORE mode).
Now, talking about this jitter... I don't think it has any relation to this
adjustment, and it's probably not going to be fixed by setting this adjustment
right.
I hope I was able to help you somehow.
KRgrds,
Fabio
On Tue, Jul 3, 2018 at 10:08 am, Colin Herbert wrote:
I have got through the calibration/adjustment procedure up to "Storage
Triggering". My problems now are twofold. I can't understand Section #3 -
"Check/Adjust Storage NORM Trigger DC Balance" (P4-89 in the manual). Apart
from the fact that the storage triggering has a deal of jitter, I can't get
step (e) to make sense. I am supposed to "use the A TRIGGER LEVEL to align
the
point where the sine-wave's leading edge intersects the center horizontal
graticule line with the 2nd vertical graticule line". Because of the the
jitter and the fact that the triggering fails when I adjust the A TRIGGER
LEVEL, this is impossible. Am I doing something wrong (quite possible), or is
the manual giving me the wrong information? Help!
If anyone has an idea of how I can eliminate the jitter, that would be nice,
too. There is no jitter in "NON STORE" operation. I was hoping it would just
be something simple like a switch needing cleaning, or an IC needing
reseating, but nothing has given me any clues so far...
Colin.
|
Re: 468 DSO Calibration/troubleshooting
Hello Collin,
Regarding my last statement (the P.S.), that this check should be made in "non-store" mode, I'm giving second thoughts at it.
I`m not sure yet, but I just found out that there are two "NORM triggering DC balance" adjustments... one on the analog side and another one on the storage side...
So, it seems weird that we could even be able to adjust the STORAGE NORM triggering DC balance in any mode that isn't a storage mode.
On the other hand, I may still be correct on my initial assumption, because the flow of the instructions and the explicit instruction to set "NON STORE" to ON, at Section #2, step g.
I`m only not sure if that adjustment (R126) would be even doable while in NON STORE mode...
I`ll get back to it as soon as I can dig a little bit more on the manual.
Rgrds,
Fabio
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On Thu, Jul 5, 2018 at 08:23 am, Fabio Trevisan wrote:
Hello Colin,
I don't own a 468 and have no particular experience with it, but I have the
manuals (in PDF form) and since your doubt is related to understaing of the
instructions, I decided to give it a try and see if I could make sense out of
this part of the instruction that you're doubtful at.
At this step, the only thing that doesn't seem really clear to me is why it
asks specifically to align the leading edge of the sine-wave to the 2nd
graticule line (why the 2nd.???)..
But, regardless of not understanding that, I think the purpose of this
calibration step is clear... Is to make a "differential" assessment of the
triggering level shift, between using AC triggering coupling and DC triggering
coupling...
So, basically what it is asking for, is for you to make sure that the
triggering point doesn't move between AC and DC coupling, when you're actually
feeding a signal that already swings about 0V...
I mean, if the input signal is swinging about 0V (i.e. if it doesn't contain a
DC level), changing the triggering coupling from AC to DC should not make any
difference, and therefore, the triggering point, whatever it was set to before
switching to DC, the wave form must remain in the same position.
If the waveform shifts horizontally, than it means that the triggering point
"seen" by the triggering circuit have changed when switching over from AC to
DC, which it shouldn't.
Giving second thoughts to the instruction, it's not much different than
adjusting the Norm DC triggering balance of a 464 (which I own), and probably
the same as the 465 (more common).
the only difference is that, for the 464, we're asked for looking at the very
beginning of the sweep, and not at the 2nd vertical graticule line (i.e. 1
division after the sweep actually started).
This difference in procedure (from the non store scope), doesn't actually
matter to what the DC balance adjustment is doing (which is nothing more than
shifting the DC level of the actual signal being fed to the triggering input
buffer, with the intent to making it match with the level of the same signal
when AC coupled).
The only reason I think they're doing that (adjusting at the 2nd vertical
graticule line iso at the beginning of the sweep), is because this point is
about the actual point on the display where the triggering point of the
digital stored signal is supposed to be displayed.
P.S. Also note that, although this adjustment step is called "Check / Adjust
STORAGE NORM Trigger DC balance", by following the instructions coming from
the previous steps, I understand (it's my conclusion though) that this
adjustment is not meant to be performed in storage mode.
The previous section, "#2 Check A and B+ gates", at step g. it asks you to
set the "NON STORE" button to ON position... and then it doesn't ever ask you
to change it to OFF, so, by the flow of the procedure, the #3 check is to be
performed in NON STORE mode.
Therefore, this jitter that you mentioned you're getting on storage mode
should not interfere with you performing this adjustment (because it's done in
NON STORE mode).
Now, talking about this jitter... I don't think it has any relation to this
adjustment, and it's probably not going to be fixed by setting this adjustment
right.
I hope I was able to help you somehow.
KRgrds,
Fabio
On Tue, Jul 3, 2018 at 10:08 am, Colin Herbert wrote:
I have got through the calibration/adjustment procedure up to "Storage
Triggering". My problems now are twofold. I can't understand Section #3 -
"Check/Adjust Storage NORM Trigger DC Balance" (P4-89 in the manual). Apart
from the fact that the storage triggering has a deal of jitter, I can't get
step (e) to make sense. I am supposed to "use the A TRIGGER LEVEL to align
the
point where the sine-wave's leading edge intersects the center horizontal
graticule line with the 2nd vertical graticule line". Because of the the
jitter and the fact that the triggering fails when I adjust the A TRIGGER
LEVEL, this is impossible. Am I doing something wrong (quite possible), or is
the manual giving me the wrong information? Help!
If anyone has an idea of how I can eliminate the jitter, that would be nice,
too. There is no jitter in "NON STORE" operation. I was hoping it would just
be something simple like a switch needing cleaning, or an IC needing
reseating, but nothing has given me any clues so far...
Colin.
|
Re: PG506 trig out jitter?
I was surprised that the PG506 manual has no reference to cable loading on the high amplitude output. The output impedance is specified as 600ohm and just over a metre of RG58 has a capacitance of 100pF so the time constant is 60ns. However 10% to 90% is more like two exponential time constants (there may be an engineering conversion factor but this is a physicist writing!). My PG506 may be below spec since I see about 140ns, 10 - 90% with about 50cm of cable.
Roger
|
Re: 468 DSO Calibration/troubleshooting
Hello Colin,
I don't own a 468 and have no particular experience with it, but I have the manuals (in PDF form) and since your doubt is related to understaing of the instructions, I decided to give it a try and see if I could make sense out of this part of the instruction that you're doubtful at.
At this step, the only thing that doesn't seem really clear to me is why it asks specifically to align the leading edge of the sine-wave to the 2nd graticule line (why the 2nd.???)..
But, regardless of not understanding that, I think the purpose of this calibration step is clear... Is to make a "differential" assessment of the triggering level shift, between using AC triggering coupling and DC triggering coupling...
So, basically what it is asking for, is for you to make sure that the triggering point doesn't move between AC and DC coupling, when you're actually feeding a signal that already swings about 0V...
I mean, if the input signal is swinging about 0V (i.e. if it doesn't contain a DC level), changing the triggering coupling from AC to DC should not make any difference, and therefore, the triggering point, whatever it was set to before switching to DC, the wave form must remain in the same position.
If the waveform shifts horizontally, than it means that the triggering point "seen" by the triggering circuit have changed when switching over from AC to DC, which it shouldn't.
Giving second thoughts to the instruction, it's not much different than adjusting the Norm DC triggering balance of a 464 (which I own), and probably the same as the 465 (more common).
the only difference is that, for the 464, we're asked for looking at the very beginning of the sweep, and not at the 2nd vertical graticule line (i.e. 1 division after the sweep actually started).
This difference in procedure (from the non store scope), doesn't actually matter to what the DC balance adjustment is doing (which is nothing more than shifting the DC level of the actual signal being fed to the triggering input buffer, with the intent to making it match with the level of the same signal when AC coupled).
The only reason I think they're doing that (adjusting at the 2nd vertical graticule line iso at the beginning of the sweep), is because this point is about the actual point on the display where the triggering point of the digital stored signal is supposed to be displayed.
P.S. Also note that, although this adjustment step is called "Check / Adjust STORAGE NORM Trigger DC balance", by following the instructions coming from the previous steps, I understand (it's my conclusion though) that this adjustment is not meant to be performed in storage mode.
The previous section, "#2 Check A and B+ gates", at step g. it asks you to set the "NON STORE" button to ON position... and then it doesn't ever ask you to change it to OFF, so, by the flow of the procedure, the #3 check is to be performed in NON STORE mode.
Therefore, this jitter that you mentioned you're getting on storage mode should not interfere with you performing this adjustment (because it's done in NON STORE mode).
Now, talking about this jitter... I don't think it has any relation to this adjustment, and it's probably not going to be fixed by setting this adjustment right.
I hope I was able to help you somehow.
KRgrds,
Fabio
toggle quoted message
Show quoted text
On Tue, Jul 3, 2018 at 10:08 am, Colin Herbert wrote:
I have got through the calibration/adjustment procedure up to "Storage
Triggering". My problems now are twofold. I can't understand Section #3 -
"Check/Adjust Storage NORM Trigger DC Balance" (P4-89 in the manual). Apart
from the fact that the storage triggering has a deal of jitter, I can't get
step (e) to make sense. I am supposed to "use the A TRIGGER LEVEL to align the
point where the sine-wave's leading edge intersects the center horizontal
graticule line with the 2nd vertical graticule line". Because of the the
jitter and the fact that the triggering fails when I adjust the A TRIGGER
LEVEL, this is impossible. Am I doing something wrong (quite possible), or is
the manual giving me the wrong information? Help!
If anyone has an idea of how I can eliminate the jitter, that would be nice,
too. There is no jitter in "NON STORE" operation. I was hoping it would just
be something simple like a switch needing cleaning, or an IC needing
reseating, but nothing has given me any clues so far...
Colin.
|
Re: PG506 trig out jitter?
Hi Siggi,
Yeah - I aped the Tek design that uses the Hi Ampl output, I guess the slow
rise leads to jitter.
Aha, that also explains why you can observe the leading edge which produced the trigger. The unterminated rise time of Hi Ampl is specified as < 100ns. Your TD probably fires at a fairly high input voltage, so the delay could easily be 50-up ns or so. That's enough (with other delays). Jitter can also be due then to your pulser instead of instability of the Hi Ampl waveform. Albert
|
Re: PG506 trig out jitter?
On Thu, 5 Jul 2018 at 02:53 Roger Evans via Groups.Io <very_fuzzy_logic= [email protected]> wrote: I tried my very early PG506 with a 7904 / 7A29 or 7A16p / 7B92A. I can't
measure any jitter between the trigger output and the fast rise outputs at
the 50-100psec level. The rise time of the high amplitude output into
50ohm is about 10nsec and due to the time delay between the trigger and
high amplitude pulse I have to use the delayed sweep on the 7B92A to get to
1nsec/div so more uncertainty but the jitter is at the 100ps or less
level. 1.5nsec sounds like something badly wrong.
Thanks, I'm looking at the output of the pulser which is after the hi-ampl output. I should look at the output of the PG506 directly.
|
Re: PG506 trig out jitter?
On Thu, 5 Jul 2018 at 05:35 Albert Otten <aodiversen@...> wrote: The PG506 specs mention delay time 18 ns between trigger out and Hi Ampl
pulse out. I don' know of course how much delay time is added by your home
made pulse generator. But if you didn't deliberately build in a delay there
then the total delay time likely as much less than required to see the
same-as-triggered-on leading edge at the sampling combination. Hence you
might be looking at the leading edge of the next pulse and jitter will
include the between-pulses jitter of the PG506.
On the 2467 I'm looking at the edge right after the trigger, and I'm pretty sure the 7S12/S-53 is also looking at the first edge. Small Tek TD pulse generators were driven by the scopes calibrator output
or unterminated PG506 Hi Ampl output, with relatively slow rise times.
Roger looked at the terminated Hi Ampl output. What is your design?
Yeah - I aped the Tek design that uses the Hi Ampl output, I guess the slow rise leads to jitter.
|
Looking for DAS9200 92A60/90 User Manual: PN: 070-5949-0x.
Hi to All,
Still looking for this Module User Manual. The only item I could find isn't available for those outside the US. Anybody?
Greetings,
Egge Siert
|
Re: PG506 trig out jitter?
Hi Siggi, The PG506 specs mention delay time 18 ns between trigger out and Hi Ampl pulse out. I don' know of course how much delay time is added by your home made pulse generator. But if you didn't deliberately build in a delay there then the total delay time likely as much less than required to see the same-as-triggered-on leading edge at the sampling combination. Hence you might be looking at the leading edge of the next pulse and jitter will include the between-pulses jitter of the PG506. Small Tek TD pulse generators were driven by the scopes calibrator output or unterminated PG506 Hi Ampl output, with relatively slow rise times. Roger looked at the terminated Hi Ampl output. What is your design? Albert
Hi Siggi,
I tried my very early PG506 with a 7904 / 7A29 or 7A16p / 7B92A. I can't
measure any jitter between the trigger output and the fast rise outputs at the
50-100psec level. The rise time of the high amplitude output into 50ohm is
about 10nsec and due to the time delay between the trigger and high amplitude
pulse I have to use the delayed sweep on the 7B92A to get to 1nsec/div so more
uncertainty but the jitter is at the 100ps or less level. 1.5nsec sounds like
something badly wrong.
Roger
as reply to
I have a little shop-made TD pulser I drive off my PG506 high ampl output.
I also now have a 7S12 with an S-4 and an S-53, so I figured I'd be able to
look at the rise of my pulser, as the PG506 has a TRIG OUT. When I pulled in close, however, it was all fuzz on the sampling gitup. Initially I figured my newly ePrayed S-53 might be wonked out, but I'm seeing the same thing on the venerable 2467.
Looks like ~1.5ns of jitter - is this typical?
Siggi
|
Re: PG506 trig out jitter?
Hi Siggi,
I tried my very early PG506 with a 7904 / 7A29 or 7A16p / 7B92A. I can't measure any jitter between the trigger output and the fast rise outputs at the 50-100psec level. The rise time of the high amplitude output into 50ohm is about 10nsec and due to the time delay between the trigger and high amplitude pulse I have to use the delayed sweep on the 7B92A to get to 1nsec/div so more uncertainty but the jitter is at the 100ps or less level. 1.5nsec sounds like something badly wrong.
Roger
|
Hey y'all,
I have a little shop-made TD pulser I drive off my PG506 high ampl output.
I also now have a 7S12 with an S-4 and an S-53, so I figured I'd be able to
look at the rise of my pulser, as the PG506 has a TRIG OUT. When I pulled
in close, however, it was all fuzz on the sampling gitup.
Initially I figured my newly ePrayed S-53 might be wonked out, but I'm
seeing the same thing on the venerable 2467.
Looks like ~1.5ns of jitter - is this typical?
Siggi
|
Hello Russ, My comments just after yours, below... Rgrds, Fabio On Mon, Jul 2, 2018 at 09:16 pm, musicamex wrote: Hi Fabio, Thanks for your comments. The film cap seemed like it was zdded
as a repair attempt and wasn't particularly large. Maybe 7 mm square and
clearly marked 47 mf. Like a small blue chicle. I have lots of similar
sized caps for use as tone caps but of less capacitance. They are usually
of higher voltage ratings. I believe this one was 63v. Ill check to see if
i tossed it. Hmmm, "Small blue chicle", to me, this shape resembles very well a dipped tantalum capacitor...but I agree with you that someone must have changed it, because the usual dipped tantalum capacitor Tek employed on this period would be color coded (striped) and wouldn't have the value marked numerically... (the page 4-4 of your manual have a graphic description of how the color coding of the dipped tantalum capacitors were). But definitely, your description fits how the regular commercial dipped tantalum capacitors are usually marketed, a single color blob, usually mustard or blue, with value marked in numbers. Sometimes, the voltage is also marked, sometimes it's omitted or it's coded on the color of the body. A 7 square mm mylar (or 7 x 7) cap could never be 47uF... I have 8.2uF mylar caps that are 30mm x 20mm x 8mm, and they're just 100V. OK that it would surely be smaller, for a smaller voltage but it would never be that small (and my example is just 8.2uF) The - 8v is the only rail that is still low. Ill do some further testing
tomorrow hopefully. We can get some pretty close lightning strikes during
our monsoon season and that can cut into my bench time. Yep, keep away from opened electrical equipment those times... It surely can be a shocking experience! We also have a lot of thunderstorms in Brazil. My wife is in the
states for a month also and it takes allot for me to also keep up with what
she does for us too. Seen that! Been there too! We miss them! I did take time to watch Brazil ice Mexico today. We're used to it by now. At least now I know someone from Brazil to
congratulate on a good game. Good luck on the next games. Thanks! Belgium won't be easy! I'll report my findings and will certainly have questions, but it seems the
logical next step is to clean out the trash in the -8v rail. I agree... The -8V is surely the next enemy to fight. To ease up the chase, try to see what can be possibly disconnected (e.g. unpluggable connectors). Right out of my mind, I think of the power connector to the Vertical amplifier board...There's -8 going in there, and you can rule that board out by simply pulling out the power supply connector (from the Vertical Output Amplifier board). Another one, is the power supply cable that goes to the Vertical Preamplifier board... The power cable (a flat colored one, IIRC of 4 or 5 wires), is soldered directly(without a connector) to the solder side of the preamplifier board and, at its other end, it goes in between the preamplifier board and the bottom, large main board (the so called interface board), and ends in a 4 or 5 pin "harmonica" connector, that you can disconnect, ruling out another possible cause for the -8V being brought down. BTW, you will see the "harmonica" term on the group discussions quite often... They're inline connectors, with 0.1 inch pitch, and they look like a small harmonica flute. They're infamous because Tek used a lot of them on the scopes of this period and, although they could have keyed them to avoid inverted and/or shifted insertion, Tek almost never did it so, you guess it, a lot of people already zapped a lot of boards and Tek made unobtanium ICs, by just carelessly inserting those harmonica connectors inverted or shifted by one or two pins. And before you ask, Yes, they ARE visually keyed. There's always a clear visual indication, both at the board and at the connector itself for which one is the #1 pin... but they're only visual... You need to assertively look for the visual keys and make sure they're aligned! Rgrds, Fabio Thx, Russ
On Monday, July 2, 2018, Fabio Trevisan <fabio.tr3visan@...> wrote:
Hello Russ,
Glad to hear that the +15V PS woke up, and by consequence, the +5V and
also, somewhat, the -8V (although this one is clearly on the lack).
I have two comments...
1. I got confused by some post of another member, after yours #149308,
still providing suggestions for the low +55V condition... as if it would
still be on the low side.
This takes me to conclude that it's not very clear to everybody there's
nothing wrong anymore, either with the +55V, or with the +15V.
Maybe you can elucidate a little on that to avoid further misunderstanding.
I`m also somewhat puzzled by the description of the capacitor you found
guilty at the C1549 position.
There couldn't be a mylar capacitor there... first because a 47uF mylar
capacitor would be humongous and wouldn't even fit in that space... second
because it would be very unlikely to fail under such low voltage... The
least voltage I've ever seen a film capacitor was something like 63V.
Well, me puzzled or not... it seems you grabbed the bulls by the horn.
Cheers for that.
2. Regarding the -8V power supply... I'm afraid that, while you were so
lucky on the +15V side, to find the shorted culprit in the very first
attempt, you may not be so lucky this time... First because it's not a
"dead short"... it can be just something drawing too much current (such as
another decoupling capacitor), or maybe the -8V power supply is at fault.
Anyway, when you find a wrong power supply rail, there's not much
troubleshooting advice than to hunt down the power sucker... it can be
anything connected to that particular rail.
Sometimes you're lucky and that supply is distributed through connectors
and cables... and in such case, you can rule-out possible culprits by just
lifting the pin on the connector, narrowing down the number of places to
look for possible culprits.
The -8V power supply looks rather unintuitive, because they chose to make
it a "positive supply", and hook the "regulated" positive output to ground,
while taking the negative output from the "unregulated" output of the
rectifier and bulk capacitor.
But other than that, it is and it works exactly the same as the +15V
supply, and the troubleshooting is also the same, just transposing the
measurements to the corresponding components.
Kindest Rgrds,
Fabio
P.S. Sorry for your fellow folks there in MEX. Today was our lucky day
(I`m Brazilian).
On Fri, Jun 29, 2018 at 10:57 am, musicamex wrote:
One step closer! C1549 looked like it might have been replaced with a
mylar
cap. As soon as I unsoldered one side and turned on the scope, the fan came
on! So i replaced it with a 47mf 25 v electrolytic and now had a bit of a
trace but way off vertical axis. Good call Albert!
The voltages now are112.5, 55.66, 15.1, 4.9 and -6.4
I see that the vertical axis is associated with the -8 rail and read the
troubleshooting for vertical axis anomalies but before I go further I thought
I check for advice here first.
Thanks in advance, Russ
--
Good judgement comes from experience; experience comes from bad judgement.
99 times out of 10 a blown fuse is not due to a bad fuse.....
|
Re: 7912AD Fails start-up self-test (perhaps)
I remember seeing 7912ADs and HBs in final test and Cal. They would use
them lead that had holes drilled in it for all the adjustments and test
points. today at wouldn't be hard to use a piece of luck Sanders just a
sheet of scrap aluminum. But what the 7912 you do want to make sure there's
air moving across everything
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On Wed, Jul 4, 2018, 10:44 AM Adrian <Adrian@...> wrote: Hi Craig,
That's not an odd question at all, it's one that I should have asked
myself before thinking about blown racks!
The fan pulls air in (quite a lot of it), through the PSU module which
then exhausts through a wide horizontal slot low down on the module
front face. From there it effectively blows between a gap under the
'widthways' cardframe carrying the PSU interface and MPU cards and
thence into the 'open' end of the 'longways' cardframe carrying the
other seven cards among which, perhaps significantly, is the video
processor and scan control card. The chassis vents at the top, front
half of each side panel so the airflow is along the cardframe
backplanes, up between the cards and across the top front then out the
sides.
So by running with no top panel I may well have short circuited the flow
by allowing most of the flow to escape to atmosphere from the top of the
first frame and prevented any effective cooling of the second?
I will replace the panel, test and report - I was contemplating doing a
temperature test under controlled conditions but turns out this beast is
too long for my environmental chamber!
Adrian
On 7/4/2018 5:26 PM, Craig Sawyers wrote:
Here's what may seem an odd question - does the rear fan pull air in, or push it out?
Craig
My 7912AD runs happily with no extra cooling, I think the interior
layout is designed to pull air
past the
major boards
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Re: 7912AD Fails start-up self-test (perhaps)
Hi Craig,
That's not an odd question at all, it's one that I should have asked myself before thinking about blown racks!
The fan pulls air in (quite a lot of it), through the PSU module which then exhausts through a wide horizontal slot low down on the module front face. From there it effectively blows between a gap under the 'widthways' cardframe carrying the PSU interface and MPU cards and thence into the 'open' end of the 'longways' cardframe carrying the other seven cards among which, perhaps significantly, is the video processor and scan control card. The chassis vents at the top, front half of each side panel so the airflow is along the cardframe backplanes, up between the cards and across the top front then out the sides.
So by running with no top panel I may well have short circuited the flow by allowing most of the flow to escape to atmosphere from the top of the first frame and prevented any effective cooling of the second?
I will replace the panel, test and report - I was contemplating doing a temperature test under controlled conditions but turns out this beast is too long for my environmental chamber!
Adrian
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Show quoted text
On 7/4/2018 5:26 PM, Craig Sawyers wrote: Here's what may seem an odd question - does the rear fan pull air in, or push it out?
Craig
My 7912AD runs happily with no extra cooling, I think the interior layout is designed to pull air
past the
major boards
|
Re: 7854 readout does not conform to specification? (7L5 problem)
On Wed, Jul 4, 2018 at 1:20 PM, zenith5106 <hahi@...> wrote: The same article (as 7L5) was also in the 7854 archive. There were no other specifically for this problem There was another about readout issues which may, or more likely, may not fix your problem. You can find it here: /H?kan I just checked and my 7854 already has this mod, so I'm out of luck. Thanks for sharing the mod anyway. I suppose this problem is in the firmware (ROM), since it's the CPU that decodes the readout and sets the scale factor. Unless there's documentation or anybody familiar with 7854 ROM content, I doubt there's anything that can be done about it. Best Regards, Nenad Filipovic
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Re: 7912AD Fails start-up self-test (perhaps)
Here's what may seem an odd question - does the rear fan pull air in, or push it out?
Craig
toggle quoted message
Show quoted text
My 7912AD runs happily with no extra cooling, I think the interior layout is designed to pull air
past the
major boards
|
Re: 7912AD Fails start-up self-test (perhaps)
Adrian,
My 7912AD runs happily with no extra cooling, I think the interior layout is designed to pull air past the major boards. I have had it running for a couple of hours with no problems. The graticule and main intensities change markedly in the first 10 minutes or so but this is mentioned in the manual.
Most of your images that look 'wrong' have multiple spots rather than continuous traces and I notice you still have the graticule turned on even though the brightness is fairly minimal. One image shows a graticule with rotated and misplaced spots. Try turning the graticule intensity down to minimum, that should turn the graticule generator off and remove one of the possible culprits.
When it is working it looks really good!
Roger
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Re: Parting out 465 (not B) and a 464
On Tue, 03 Jul 2018 22:46:01 -0700, you wrote: Hi Keith,
If you have the extension shaft to pot couplers available, I'd be very interested. They are the cast aluminum with plastic insert ones with 2 #4 set screws, like on the "var" knobs on the voltage combo controls. I have 2 that are broken that i cobbled together some Mexico style repairs on. One with shrink tube because the plastic was broken, the other with a brass standoff that i drilled and tapped. I could probably use a few other small parts too. Like the cord wrap plastic tabs. I'll look up the proper names if you want me to. If they are the same as the ones in a 7A18, 7A26 and so on, I may have some. What's the shaft diameter? Harvey
Thanks, Russ
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Re: 7912AD Fails start-up self-test (perhaps)
Hmm, I think we are getting there! See 'Getting there'* in album: /g/TekScopes/album?id=62098&p=Name,,,20,1,0,0 So what did I do? Well not a lot except move the stuff to a different bench and, more importantly I suspect, switched things on early today before the sun moved round - well, ok it stayed still(ish) but the planet rotated - and started warming up the barn. It ran happily for about 15 minutes then collapsed in a heap again, let it cool off for 5 minutes and it ran for a couple more then failed again. So something is getting hotter than it likes. There is no cooling in this thing other than in the PSU, I wonder if it was assumed it would be mounted in a blown rack? I've put it up on blocks with a desk fan blowing across it and we'll see if that helps but I'm going to swap out all the tant caps I can see on A38 and A28 for a start! * Sorry about the Non-Tek scopery lurking in the background - hope I don't get struck off! Thanks again for all the help and advice, Adrian
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Re: 7854 readout does not conform to specification? (7L5 problem)
I'm sure this problem is fully on the 7854 side. Do by any chance these WW
articles have any info on 7854 readout mods? Any hint where I could
find/download them?
Best Regards,
Nenad Filipovic The same article (as 7L5) was also in the 7854 archive. There were no other specifically for this problem There was another about readout issues which may, or more likely, may not fix your problem. You can find it here: /H?kan
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Fabio Trevisan
zenith5106