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Re: New member I need help to create a symbol

 

¿ªÔÆÌåÓý

I didn't see an option where to save it, but I didn't look for one. I will investigate.

======================================================================================
Best wishes John Woodgate OOO-Own Opinions Only

Rayleigh, Essex UK

I hear, and I forget. I see, and I remember. I do, and I understand. Xunzi (340 - 245 BC)


On 2023-03-29 20:50, Steven A. Falco wrote:

I just tried this on a Win11 virtual machine with KiCad 6.0.11.? In the symbol editor I clicked "New Library" and it defaulted to creating "RMS detector" in C:\Users\sfalco\Documents\KiCad\6.0\symbols which is writable.? If you are trying to add a library to the system library folder, that might not be writable, but I don't see why KiCad would default to that.

Do you get the option to select where to put the library?


Re: New member I need help to create a symbol

 

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That is probably in a subfolder from c:\Program Files\KiCad where you have no rights to write.

Op 29-3-2023 om 21:29 schreef John Woodgate:

KiCad 6.0 on Windows 10. I didn't specify a path for saving, I just added the new Library to the Library folder.

======================================================================================
Best wishes John Woodgate OOO-Own Opinions Only

Rayleigh, Essex UK

I hear, and I forget. I see, and I remember. I do, and I understand. Xunzi (340 - 245 BC)


On 2023-03-29 20:09, Steven A. Falco wrote:
Which version of KiCad are you using?? Also, is this on Windows, Linux, or Mac?

I am using Linux, and by default KiCad saves to ~/.local/kicad/7.0, but I can specify a different path if I prefer.

-- 
IDcircuits - RFID & Electronics
Het Halster 40
6581 JL Malden
The Netherlands
+31 633702492

r.gerritsen@...


Re: New member I need help to create a symbol

 

I just tried this on a Win11 virtual machine with KiCad 6.0.11.? In the symbol editor I clicked "New Library" and it defaulted to creating "RMS detector" in C:\Users\sfalco\Documents\KiCad\6.0\symbols which is writable.? If you are trying to add a library to the system library folder, that might not be writable, but I don't see why KiCad would default to that.

Do you get the option to select where to put the library?


Re: New member I need help to create a symbol

 

¿ªÔÆÌåÓý

KiCad 6.0 on Windows 10. I didn't specify a path for saving, I just added the new Library to the Library folder.

======================================================================================
Best wishes John Woodgate OOO-Own Opinions Only

Rayleigh, Essex UK

I hear, and I forget. I see, and I remember. I do, and I understand. Xunzi (340 - 245 BC)


On 2023-03-29 20:09, Steven A. Falco wrote:

Which version of KiCad are you using?? Also, is this on Windows, Linux, or Mac?

I am using Linux, and by default KiCad saves to ~/.local/kicad/7.0, but I can specify a different path if I prefer.


Re: New member I need help to create a symbol

 

Which version of KiCad are you using?? Also, is this on Windows, Linux, or Mac?

I am using Linux, and by default KiCad saves to ~/.local/kicad/7.0, but I can specify a different path if I prefer.


New member I need help to create a symbol

 

¿ªÔÆÌåÓý

I am trying to create a symbol for the AD736 RMS detector, but I am having no success either creating a new symbol or modifying an existing one (NE555). I created a library 'RMS detector', but I am told that it is not writeable, so I can't create or modify a symbol.

--
======================================================================================
Best wishes John Woodgate OOO-Own Opinions Only

Rayleigh, Essex UK

I hear, and I forget. I see, and I remember. I do, and I understand. Xunzi (340 - 245 BC)



Re: Netclass directives in hierarchical design failing to resolve.

 

Can you please report a bug with this project attached?

On Thu, Mar 23, 2023 at 9:25?AM Jason Bens <jason@...> wrote:
Hi,

I have a design I'm working on that has a couple high voltage traces.? I wanted to denote this graphically with a net class directive.? What I've found, though, is that the resolved netclass for this trace is Default, regardless of whether I place the directive on the super- or sub-page.? The only way I've gotten it to resolve correctly is when I place the directive on every sheet where the signal appears, which I'm not a fan of.? Is this the only way to make it work?

The ERC should also probably catch this error, which it currently?isn't.? While I don't know what's happening under the hood, it seems like it should be treated similarly to a conflicting netclass assignment.

ERC catches this error:
image.png
ERC fails to catch this error.? Note that both cases resolved to Default:
image.png
Removing the hierarchical?connector makes it resolve as expected.
image.png
For these three examples, the sheet pin was present one sheet up, but the signal was left unconnected without a netclass assigned at this level.

?- Jason

--
Jason Bens
Product Design & Engineering
?
?|? ?|? t:?+49 160 273 86 34
HRB 239206 B, Amtsgericht Charlottenburg(Berlin), Gesch?ftsf¨¹hrer: Gerard Sanders und Tim Dieryckx.


Netclass directives in hierarchical design failing to resolve.

 

Hi,

I have a design I'm working on that has a couple high voltage traces.? I wanted to denote this graphically with a net class directive.? What I've found, though, is that the resolved netclass for this trace is Default, regardless of whether I place the directive on the super- or sub-page.? The only way I've gotten it to resolve correctly is when I place the directive on every sheet where the signal appears, which I'm not a fan of.? Is this the only way to make it work?

The ERC should also probably catch this error, which it currently?isn't.? While I don't know what's happening under the hood, it seems like it should be treated similarly to a conflicting netclass assignment.

ERC catches this error:
image.png
ERC fails to catch this error.? Note that both cases resolved to Default:
image.png
Removing the hierarchical?connector makes it resolve as expected.
image.png
For these three examples, the sheet pin was present one sheet up, but the signal was left unconnected without a netclass assigned at this level.

?- Jason

--
Jason Bens
Product Design & Engineering
?
?|? ?|? t:?+49 160 273 86 34
HRB 239206 B, Amtsgericht Charlottenburg(Berlin), Gesch?ftsf¨¹hrer: Gerard Sanders und Tim Dieryckx.


Re: KiCad roadmap

 

I found this with a search engine, but it only seems to go as far as
Kicad 6:



Regards,

Robert.

* Plain text email - safe, readable, inclusive. *

On 01/03/2023 20:23, Chris via groups.io wrote:
Does KiCad publish its roadmap for guiding future development publicly? If so, can someone please provide a link to it.

Thanks.





KiCad roadmap

 

Does KiCad publish its roadmap for guiding future development publicly? If so, can someone please provide a link to it.

Thanks.


Original author of KiCAD: Jean Pierre Charras

 

out of curiosity: do you have any pictures and more information about the original author of KiCAD? Mr Jean Pierre Charras. I'm looking for a picture of him and I can't find it. I'm writing a book


Kicad 7

 

Have been using Kicad 6 for some time.? I installed Kicad 7 and a project I am working on has four different pcb designs.? All were designed using Kicad 6.? 3 of the boards migrated fine into Kicad 7 and I can edit the boards etc. However, one board does not allow me to edit it in Kicad 7, all tracks, vias and components are highlighted in purple and the lock/unlock toolbar options are greyed out.? It is though something has completely locked up the design and I see no way to unlock it.

TIA,

Tony Osman


PCBNew User Layer change on top/bottom

 

¿ªÔÆÌåÓý

Hello

I have developed a technique to make my own paste screens using hobby cutting machine (Cricut).

These machines lack the resolution to create a proper paste screen but, after experimentation I have discovered I can get acceptable results for home SMT assembly by using a custom shape. I can regularly solder TQFP-48s, 0603 resistor networks, and so on, without any issues. Rather than modifying the paste layer of the footprint, which may cause issues if I get the boards professionally manufactured, I make my own "special" paste mask (see the picture below. I place this on layer User 1. The problem is, when I plot, Layer 1 is plotted on the top and bottom.

I guess I could make a User1 and User2 but I was wondering if there was another way.

Thanks




Re: Vida to Path clearance

 

Have you ever dealt with a Chinese factory directly? There is a reason why pcb brokers are still here. Sometimes, communicating with them is just bad. Even pcbway can't even get their specs straight when you ask about it. You say also that they are ambiguous on finished vs drilled....well how do you think they feel when customers do not know specify finished vs drilled?


On Fri, Feb 3, 2023, 11:51 AM Rick Collins <gnuarm.2007@...> wrote:
Hole to hole clearance(Different nets)
Via to Via clearance(Same nets)
Pad to Pad clearance(Pad with hole, Different nets)

Yes, these all have the same drawing, but they are different types of structures.? What bugs me is they are actually talking about the holes for the structures, but simply say "via" or "pad" rather than specifying the drill hole.? I chalk this up to language issues. What would you expect to see different in the three drawing??

I also don't appreciate that they leave as ambiguous whether the hole is the finished hole, or the drilled hole.? I would expect it to be the drilled hole for any sort of clearance, but who knows what they are doing if they don't tell you?

Why would "Via to Track" be different from "PTH to Track", but the same as "NPTH to Track"??

With the volume they produce, you would think they might put more effort into effective communication.

--

Rick Collins

? - Get 1,000 miles of free Supercharging
? - Tesla referral code -


Re: Vida to Path clearance

 

Hole to hole clearance(Different nets)
Via to Via clearance(Same nets)
Pad to Pad clearance(Pad with hole, Different nets)

Yes, these all have the same drawing, but they are different types of structures.? What bugs me is they are actually talking about the holes for the structures, but simply say "via" or "pad" rather than specifying the drill hole.? I chalk this up to language issues. What would you expect to see different in the three drawing??

I also don't appreciate that they leave as ambiguous whether the hole is the finished hole, or the drilled hole.? I would expect it to be the drilled hole for any sort of clearance, but who knows what they are doing if they don't tell you?

Why would "Via to Track" be different from "PTH to Track", but the same as "NPTH to Track"??

With the volume they produce, you would think they might put more effort into effective communication.

--

Rick Collins

? - Get 1,000 miles of free Supercharging
? - Tesla referral code -


Re: Vida to Path clearance

 

Hi, Alan!

On 2/1/23 19:01, Alan Pearce via groups.io wrote:
Yeah, well, that is most likely a chat bot with no-one on the other end. That seems to be the case with those things as I understand it.
While they use identical pictograms they DO dimension correctly for the dimension they are providing, and if one can't follow the dimension lines ...
=> Definitely: No!

I don't know at which pictures you are looking at - or what browser you use.
I was referring (I called it PictureX) to exactly
in the section "Minimum clearance" on

Which is used at least three times: Via-to-Track, PTH-to-Track, NPTH-to-Track.

Same with:
This is used three times as well: Hole-to-Hole, Via-to-Via, Pad-to-Pad.

We seem to waste time here dissecting JLCPCBs Website... come on.

Greets,

Clemens


On 2/1/23 19:01, Alan Pearce via groups.io wrote:
Yeah, well, that is most likely a chat bot with no-one on the other end. That seems to be the case with those things as I understand it.
While they use identical pictograms they DO dimension correctly for the dimension they are providing, and if one can't follow the dimension lines ...
A difference between track-pad and track-track spacing will be normal to allow for soldering of pads. Even vias will require extra space for manufacturing tolerancing.
On Wed, 1 Feb 2023 at 16:44, Clemens Koller <cko@... <mailto:cko@...>> wrote:
Hi!
The <>
are IMO inconsistent in many aspects. Identical pictograms are used
for different values, indeed leading to confusion.
And I asked the staff directly via the online chat, why there is a
difference in between track-pad (PTH) spacing vs. track-track spacing.
The answer was "pls wait"; then "still checking" and then
"The chat has been closed due to long user inactivity."
-> good luck.
Greets,
Clemens


Re: Vida to Path clearance

 



On Thu, 2 Feb 2023 at 18:45, Clemens Koller <cko@...> wrote:
Hi!

On 2/1/23 19:01, Alan Pearce via wrote:
...
>> While they use identical pictograms they DO dimension correctly
>> for the dimension they are providing, and if one can't follow the dimension lines ...

I tend to disagree:
Via-to-Track = 0.254mm = PictureX
PTH-to-Track = 0.33mm = same PictureX
NPTH-to-Track = 0.254mm = same PictureX, which, btw. shows a PTH and not a NPTH.

?
Well, you could take that annular ring as a keep out, such as one would have for a screw head on a mounting hole, but that is beside the point.

But the point I was making is that even though they show the same pad and track in each picture, they each have a seperate set of dimensioning lines to show what dimension they are referencing, and if people don't understand the way each picture has been dimensioned, how can they understand something as basic as track to track spacing, or even track width.


Re: Vida to Path clearance

 

Hi!

On 2/1/23 19:01, Alan Pearce via groups.io wrote:
Yeah, well, that is most likely a chat bot with no-one on theother end. That seems to be the case with those things as I understand it.
I had the impression there was a human at the other end.
But good point. Next time, I'll ask a sqrt(64)+34=? question before I
continue wasting my time.

While they use identical pictograms they DO dimension correctly
for the dimension they are providing, and if one can't follow the dimension lines ...

I tend to disagree:
Via-to-Track = 0.254mm = PictureX
PTH-to-Track = 0.33mm = same PictureX
NPTH-to-Track = 0.254mm = same PictureX, which, btw. shows a PTH and not a NPTH.

A difference between track-pad and track-track spacing will be normal
to allow for soldering of pads.
I disagree when details are missing.
JLCPCB's seems to be mixing up PTH / NPTH and non drilled SMT Pads.

Anyway:
It seems to be advisable to send them your data to check their rules
for you. Maybe they are right, then. Only if you get a written
commitment, you can pull the trigger to go.

I have a good set of rules for my boards settled over the years which
can be manufactured at a known set of HDI-Houses. And I know where
the limitations are of some of them. Those are mostly originates not
due to the design rules, but more like in their manufacturing process.
E-Test failed because of open Vias (aspect ratio was 8:1 and they said
they are able to do that) because there was air trapped in the Via
(A shaker/vibrator thingy in the chemical bath was broken.)
Or we had Via barrel ruptures because of a failed de-smearing process.
The E-Test was okay after manufacturing... but after soldering we
ran into failing boards... You can guess, it was an lengthly discussion
about who will be responsible for the damage.
Good that we saved soldering temperature profiles...


Greets,

Clemens


On Wed, 1 Feb 2023 at 16:44, Clemens Koller <cko@... <mailto:cko@...>> wrote:
Hi!
The <>
are IMO inconsistent in many aspects. Identical pictograms are used
for different values, indeed leading to confusion.
And I asked the staff directly via the online chat, why there is a
difference in between track-pad (PTH) spacing vs. track-track spacing.
The answer was "pls wait"; then "still checking" and then
"The chat has been closed due to long user inactivity."
-> good luck.
Greets,
Clemens


Re: Vida to Path clearance

 

Yeah, well, that is most likely a chat bot with no-one on the other end. That seems to be the case with those things as I understand it.

While they use identical pictograms they DO dimension correctly for the dimension they are providing, and if one can't follow the dimension lines ...

A difference between track-pad and track-track spacing will be normal to allow for soldering of pads. Even vias will require extra space for manufacturing tolerancing.

On Wed, 1 Feb 2023 at 16:44, Clemens Koller <cko@...> wrote:
Hi!

The
are IMO inconsistent in many aspects. Identical pictograms are used
for different values, indeed leading to confusion.

And I asked the staff directly via the online chat, why there is a
difference in between track-pad (PTH) spacing vs. track-track spacing.

The answer was "pls wait"; then "still checking" and then
"The chat has been closed due to long user inactivity."

-> good luck.

Greets,

Clemens


Re: Vida to Path clearance

 

Hi!

The
are IMO inconsistent in many aspects. Identical pictograms are used
for different values, indeed leading to confusion.

And I asked the staff directly via the online chat, why there is a
difference in between track-pad (PTH) spacing vs. track-track spacing.

The answer was "pls wait"; then "still checking" and then
"The chat has been closed due to long user inactivity."

-> good luck.

Greets,

Clemens

On 1/31/23 21:43, Alan Pearce via groups.io wrote:
What is confusing about the pictures here?
<>
Then look under minimum clearance, and the last picture seems to be what the OP is asking about.
The pad to track dimension seems to match the PTH to track dimension plus the minimum annular ring dimension, which is what I would expect.
The NPTH to track dimension will be different because there will be no annular ring (despite showing one in the picture).
On Tue, 31 Jan 2023 at 15:47, Rick Collins <gnuarm.2007@... <mailto:gnuarm.2007@...>> wrote:
You will need to ask JLCPCB then.? I've always found their web site to be confusing, with unclear terminology.? This makes no sense to me.? Copper to copper should be the same regardless of which copper it is.
--
Rick Collins
? - Get 1,000 miles of free Supercharging
? - Tesla referral code - <>