Dont forget the gate drain capacitance, whilst it may be smaller than the gate source capacitance the voltage swing across it can be large. The miller effect due to Cgd can usually be easily seen in the switching characteristics.
Bruce
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On 26 July 2018 at 20:20 satbeginner <castellcorunas@...> wrote:
Hi all,
with respect to FET's, I'd like to think of them as purely "Voltage" driven.
So, imho you're both making the same point:
If an one fet has a bigger input capacitance than the other, the drive circuit needs to be able to reach the required ON-voltage by delivering a higher current to charge the higher input capacitance of that FET.
If a FET need a higher input charge (nC) to switch on, that may be just the combination of ON-voltage and Input capacitance of that particular FET.
Basically: Q = C x V , Charge (Coulombs) = Capacitance (F) x Voltage (V)
The FET i ordered (IPA60R280E6) has a GS threshold voltage of 3-3,5V, so the 14V puse should be high enough to drive it, Voltage wise.
The original FET IRF710 has a GS threshold voltage of 4V.
I like the idea of running the chip by applying a test voltage of 28V down to 14V as used to test the chip as described in H?kan's document, and, while running, put a 1nF capacitor (imitating a worst case FET) in place of the real FET's G-S.
This way, using a second scope, I can see if the driver circuit is capable of driver this higher, capacitive load.
All this with Q9030 removed of course.
If not, I even may change (lower) R909 a bit.
A combination of R909 at 39Ohm and 200pF (original FET) would give an approximate risetime of 8ns;
A combination of R909 at 39Ohm and 1000pF (replacement FET) would give an approximate risetime of 40ns.
For now I ignore the ristime of Q908, the drive transistor in this comparison.
I will try the capacitor test later this afternoon.
Assume the switching frequency of the PS is 40kHz, thus having a period of 25us, so even with a dutycycle of 10% ON-pulses (ON-time 2,5us) the new risetime should work OK in terms of pulse duration.
The thing that might be a thingy could be the power consumption of the FET during the ON-OFF transitions, and for that reason it can be helped to increase the risetime by reducing R909 to force the FET to switch fully ON faster.
On the other hand, having a way lower ON-resistance could make up for the power consumption durig transistions
So far my thoughts, any ideas?
Un saludo,
Leo
