Ok, good new information always helps.? Looks like the processor is indeed able to measure the voltage at ADC_3V3, but I am quite confused about why the processor would be maxing out its 3V duty cycle at 27% when the voltage is higher than 3V - it seems that it should be reducing the duty cycle to reduce the voltage -- but the processor is probably confused, since its own VDD is at 2.97V (from the linear regulator), and isn't changing.? Because you have the drain of Q111 lifted, VDD and the ADC_3V3 voltages don't track.
?
The data you present gives two other issues to resolve, before restoring the drain of Q111:
?
1)? Some conflicting information to clarify/resolve: in one place you say "ADC_3V3 measures 6.6V" and another you say you measure 3.3V at ADC_3V3 (which corresponds with the 6.6V seen in the diag screen).? But you also say that Q111 source is cleanly at 10.6V.?? This doesn't quite add up: if Q111 source is at 10.6V, then ADC_3V3 must be at 5.3V (not 6.6 or 3.3), because of the resistor divider of R110 and R112.? So something is still wrong with this measurement picture, or something is interfering.
?
2) And since the voltage at Q109 Drain is not going down to 0V, it is not getting fully turned off, or it could be damaged.? I would check the voltage waveform at Q109 gate. ?R107/Q113 should be pulling the Q109 gate up to very near its source voltage when PWM_3V3 is low, which should turn off Q109. ?If this is happening, then Q109 is probably broken.? If the gate voltage is not getting that high (which I suspect is the case) then another of the PWM components isn't doing its job.? Check to make sure PWM_3V3 looks like a good pulse wave from 0V to almost 3V, and check the Q107 drain and Q113 emitter voltage waveforms to diagnose where the problem is.?
?
