Stan and Ludwig:
1)? Some conflicting information to clarify/resolve: in one place you say "ADC_3V3 measures 6.6V" and another you say you measure 3.3V at ADC_3V3 (which corresponds with the 6.6V seen in the diag screen).? But you also say that Q111 source is cleanly at 10.6V.?? This doesn't quite add up: if Q111 source is at 10.6V, then ADC_3V3 must be at 5.3V (not 6.6 or 3.3), because of the resistor divider of R110 and R112.? So something is still wrong with this measurement picture, or something is interfering.
Ah, yes, confusing. Actual measured is 3.3v at ADC 3V3. Which as you mentioned Indicates an actual VDD voltage of 6.6. But as I noticed also, the diag screen says 5.3. So no, actuals and calculated values do not add up. I also thought that 10.6 should show up as 5.3 at ADC 3V3. Maybe it is confused by the VDD actual measured being 2.97 (sourced by IC101) and ADC 3V3 being 3.3 measured indicating a VDD of 6.6v. Hopefully I didn't make it more confusing. Suffice to say. I agree...
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2) And since the voltage at Q109 Drain is not going down to 0V, it is not getting fully turned off, or it could be damaged.? I would check the voltage waveform at Q109 gate. ?R107/Q113 should be pulling the Q109 gate up to very near its source voltage when PWM_3V3 is low, which should turn off Q109. ?If this is happening, then Q109 is probably broken.? If the gate voltage is not getting that high (which I suspect is the case) then another of the PWM components isn't doing its job.? Check to make sure PWM_3V3 looks like a good pulse wave from 0V to almost 3V, and check the Q107 drain and Q113 emitter voltage waveforms to diagnose where the problem is.?
Right. On the Schem. I show the waveform at Q109 gate / Q113s emitter. It is ramping up to 12v and back all the way down to 0v, hold for a bit and repeating.
The waveform on PWM 3V3 is perfect, Q107 drain is a clean square/rectangle wave duty cycle matching the gate.
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Ludwig
Randy, something is strange. Early you wrote VDD is produced by the linear regulator. LIN_REG_EN must show some volts to connect IC101 to "+12V" via Q102. Your schematic shows 0V at LIN_REG_EN. Appropriate Diagnostics show the status SMPS. This should switch off IC101. So there maybe a (helpful) failure.
Yes. Because I lifted Q111 and D109 it has to be coming from the linear regulator. Why it is on when LIN_REG_EN is at 0v I do not know. Maybe Q102 is shorted.
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LIN_REG_EN at 0V would also switch off Q110 and R114. R114 is an artificial load to operate the SMPS without a real load. It's hard to adjust a SMPS with (nearly) no load. Maybe this is the reason for the too high voltage at D of Q109.
That is what I suspected. Drain floating in the breeze.
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A not well working Q113 may cause a similar effect. Please check the oscillogram at B of Q113. It should show rectangle from around 0V up to "+12V". The voltage at E of Q113 should follow but with around 0.7V at low and "+12V"-0.5V at high.
Nice square (rectangle) wave on the base of Q113. The wave form on the emitter is equivalent to what I see on the 5v circuit. It is shown on my schematic. Different duty cycle.
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Thanks for all of the input. I have a full complement of replacement components arriving on Thursday. We will soon find out who the culprit is.
My money is on D109 at a minimum since it won't power up at all when it is in-circuit.?
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Randy, N4OPI
