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My home build VNA uses a single SI5351 to generate both the test signal and the LO for the downmix to the audio IF where the I/Q demodulation is done.
The VNA has some problems in isolation and one possible cause is leakage from one output of the SI5351 to the other output so we should measure how good/bad this is.
One output of the SI5351 is connected to the SA with 30dB attenuation. The other output of the SI5351 is not connected. The third output is always mute and not frequency has been setup
The SW steering the SI5351 uses for each output a separate VCO to have fully independent frequency control.
Different attenuation levels where used to verify the seen signals where not created due to IMD in the SA.
First with 10MHz on one outputs and the others muted. Seems OK, all spurs are at least 70dB down.
And yes, there is a small mistake in the auto marker algorithm of the SA




Then with a second output active at 15MHz. The second output is visible at -55dB, but also a strong spur at 5 MHz (-62dB). This already explains the isolation problems in the VNA




Will it get worse at higher frequencies? First with two outputs both set to 50MHz, a nice clean signal



And now with the connected output set to 50MHz and the open output to 52MHz. The level of the spurs is only 42dB down. When you send this as LO to a mixer with a LO-IF isolation of 30dB the not connected output will appear at -72dB in the IF output of the mixer which fully explains the (lack of) isolation performance of the VNA using this SI5351?



But is this a result of the output stages doing some mixing or is it earlier? Lets test with the connected output again set to 10MHz and and the open output to 66MHz



Measurement at other frequencies have confirmed that the direct output leakage increases with increasing frequency but the other spurs (like seen above) are not directly related to the selected output frequency. The modulo? difference between the frequencies of the two outputs determines the level and position of the spurs and these follow a pattern that repeats a number of times over the total frequency range. It may be possible that the coupling/leakage is through the PLL loop in the SI5351. More to investigate.

Thoughts, feedback is welcome.

Jim,

The control lines are all terminated according to the data sheet.
Different output terminations (open/short/capacitive/50 ohm) have been tested and have maximum 5dB impact on the levels of the spurs.
Different/improved supply decoupling still has to be tested.
I did some testing with the ClockBuilder Pro SW from SiLabs and it seems the clock builder avoids using to VCO's and with one VCO whenever you have a setup that uses fractional PLL spurs you always get warnings about "possible coupling" so I guess SiLabs is well aware of the limitations.

My current setup uses two VCO's, See if I can change the SW to use only one cause maybe the spurs from fractional PLL are less then the VCO coupling problems.?
Will also check if there is some material of this on the SiLabs forum.

You're digging pretty deep here!??
Good stuff.

I've never looked closely at spurs and phase noise out of an si5351,
but did write the (very compact) routines for the uBitx,
can give 3 arbitrary <= 112.5 mhz outputs using fractional output dividers from one vco.
The ubitx does have trouble with crosstalk, one possible solution is external filters.

The G0UPL library should give you 2 outputs from 2 vco's.
The Etherkit library tries to let you do everything, but might be a bit more confusing.

The si5338 is about the same architecture, better docs, better performance.? That si5338 docs
say their fractional output dividers add less than a factor of 2 in spur power over integer output divides.
It also describes how:? They do the usual divide by m and m+1 to get a fractional divide,
but then adjust the rising and falling edges of the output using programmable delay lines,
computing the appropriate delay for each edge on the fly.

Fractional PLL divides seem to be less an issue, as there's an analog loop filter in there.
?
I've always assumed that the si5351 crosstalk was mainly due to the output buffers,
perhaps in part because of the single vcc and gnd pins.? But supply ripple and feature
proximity could cause trouble anywhere on that die.?
Your suggestion that it is back in the vco section is interesting.
?
The si5351 was meant mostly as a device to replace crystal oscillators in digital gear,
95% of their customers likely don't give a rip about a bit of crosstalk.

I've heard that if you need two outputs, best to use clk0 and clk2, leave clk1 quiet.

If the object is a working instrument, I'd probably just put down a second si5351.
If the object is solving puzzles, I guess this one is as good as any other.?
What you learn may useful for the uBitx.

Jerry, KE7ER

The si5351 can be programmed to drive unused outputs low.
That should be good enough.

After more testing some rules:

Target output is: The output required to have minimum spurs
All dB levels in the rules refer to the target output level as 0dB

- Muting an output and stopping the clock will remove all spurs from that output/clock
- Any use of fractional PLL will increase the number of spurs on ALL outputs (at < -70dB)
- Any use of fractional PLL on output next to the target output will cause substantial spurs (> - 60dB)
- Avoid any frequency close to but not exactly a multiple of 5MHz
- The spurs in multiples of 5MHz can be above -55dB

In practice:
With an IF2 at 10.7MHz, set IF1 to xx.7Mhz i.s.o. xxMHz so LO2 can be set to xx-10 MHz and make sure xx is a multiple of 5MHz

Example:
IF1 is 40MHz, LO1 is 45MHz, IF2 is 10.7MHz, LO2 is 29.3MHz


Changing the IF1 to 40.7MHz
So IF1 is 40.7MHz, LO1 is 45MHz, IF2 is 10.7MHz, LO2 is 30MHz



Of course when changing LO1? to tune differently this will cause spurs in LO1 so there is never a generic good solution for the tuning signal but all other frequencies should be multiples of 5MHz to avoid a accumulation of spurs

Forgot to mention.

The tested SI5351A uses a 25MHz XCO as reference, hence the multiples of 5MHz, will be different if you use a 27MHz XCO
The examples use output 0 for LO1 and output 2 for LO2 and keep output 1 muted low

Programming the chip to drive an unused output low, and then externally shorting that pin to ground,
will effectively give that chip a second ground.? A very good thing, since the si5351 only has one ground pin.
Could make a difference when we're talking about crosstalk 1000+ times weaker than the desired signal.
Perhaps my career as a mostly digital guy was showing there.

However, I would suggest you verify that the pin is at ground potential after the firmware has loaded it
before shorting it to ground with a wire.? On the si5351 that unused output should be clk1, between clk0 and clk2.

Jerry, KE7ER

During testing I found some impact of output loading on the crosstalk between two active outputs. But unused outputs can be set to active low and the ppl shut down and changing loading of these muted outputs has no impact on crosstalk between the active outputs.

On the SiLabs forum a support engineer explicitly states the best solution to low crosstalk is using multiple SI5351. That is what I intend to do

Hi Erik. I'm trying to make an antenna analyzer based on the si5351 but i can't accomplished. I'm using a sa612 mixer. I have to scroll in an entire frecuency range. For example 50 Mhz to 100 Mhz. I can't accomplished. I need that one output stay 1 khz higher than the other output and this can't be done yet. Can someone help me? I make a firmware for the pic18f2550. I changed the FI(intermediate frecuency) for example 10.7 Mhz.(one output at 50 Mhz and the other in 60.7Mhz) When i measured with an spectrum analyzer the 60.7 Mhz looks like 60.001Mhz. I don't know what 's wrong with my firmware

Hello

"high performance" - please define "high" . There is always cross talk in any circuit. It is only a matter of how much. Using two devices should not break the bank I guess.

antenna analyzer
- you have to run CLK0 on PLLA and CLK1 on PLLB
- have you initialized correctly?
- are you loading FMD0 + OMD0 and FMD1 + OMD1 "in pair" correctly? Per

Bo
www.rudius.net/oz2m :: www.rfzero.net

On Wed, Dec 2, 2020 at 12:17 PM, NahuelArg wrote:

Hi Erik. I'm trying to make an antenna analyzer based on the si5351 but i can't accomplished.

Can I suggest you take a look at the nanoVNA source code?
In the nanoVNA the two outputs of the SI5351 are constant 5kHz apart.
?
--
HBTE Files section:?/g/HBTE/files
Erik, PD0EK