R15 and ADE-1 mixer getting very hot
I'm testing a new bitx3c build.? When I apply 12v R15 and ADE-1ASK mixer gets extremely hot.? I removed Q7 and R11 and it still gets very hot.??? This leaves only the ADE-1ASK in the circuit.? I have replaced the mixer and still R11 gets hot.?? The ADE-1 must be drawing heavy current.? How can this be?? ADE-1 Pin 1 connects to 12v (via R11), pin 6 is an open circuit (since I removed Q7 & R11).??? I'm at a loss here, I have replaced the ADE-1ASK twice. My mixers are labeled ---------------
MCL 0414 ADE-1ASK -2 --------------- W4WHL
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Re: Issues With calibrate and TX
Use a stiff 12V supply to start.? I have not had good success with anything less than 2A.? Linear if you have it. My BitX40/v1.07 works FB.
Larry KB3CUF
On Wed, Apr 26, 2017 at 1:19 PM, Steve Greer <km4ous@...> wrote: Ok it seems strange to me but whenever I have the cal function in my code when I hit ptt to TX it goes to calibrate and then save.? I have all wires with a ground wrapped around connected from 1 end shielding all wires and twisted.? I have no other buttons going wacky just the cal function.? It even happens with the new code that came out with the multi function button.? Goes straight to calibrate and then save and knocks everything out of whack.? Anyone have this issue and any resolution? thx 73 steve
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Issues With calibrate and TX
Ok it seems strange to me but whenever I have the cal function in my code when I hit ptt to TX it goes to calibrate and then save. ?I have all wires with a ground wrapped around connected from 1 end shielding all wires and twisted. ?I have no other buttons going wacky just the cal function. ?It even happens with the new code that came out with the multi function button. ?Goes straight to calibrate and then save and knocks everything out of whack. ?Anyone have this issue and any resolution? thx 73 steve
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
Pavel, I haven't tried coding for the Si5351, you could be right. ?However, on page 3 of AN619: 3.2. Feedback Multisynth Divider Equations ? ? ? ?fvco = fxtal * (a * b/c) where ? ?a+b/c ? ?"has a valid range of 15 + 0/1,048,575 and 90 +0/1,048,575" How the multisynth dividers get described is one of my primary issues with the Si5351 docs. ? I read that to mean ?a+b/c can take on pretty much any fractional value between 15.0 and 90.0. ?I looked over some of the other Si5351 libraries available a couple years ago and concluded that the Si5351 doc did not adequately describe the the multsynth dividers. ?However, a+b/c can take on non-integer values, with the fractional part having a resolution down to one part in a million. ?It is not just a simple divider. ? As the Si5338 docs describe, this is done by having a tapped delay line that follows a divider jumping between two adjacent integer values, some math is done for each outgoing clock edge to determine the optimum delay line setting to minimize jitter for that particular edge. Since Etherkit is successfully using an external 25mhz TCXO, I suspect fxtal on an Si5351A could successfully be driven by an external oscillator with anything between 10mhz and 40mhz as suggested at the top of page 3 of AN619. ?At 10mhz the required range for a+b/c would be between 600/10 = 60.0 and 900/10=90.0. ?At 40mhz, the required range for a+b/c would be between 600/40= 15.0 and 900/40 = 22.5. ? ?That agrees nicely with the range of 15.0 and 90.0 stated previously for a+b/c. ?If using a crystal, it must be between 25 and 27mhz just to make sure the internal oscillator starts up properly. ?If using the external clock pin on the Si5351C (that expensive 20 pin QFN), you can have an external clock of up to 100mhz, using CLKIN_DIV to bring the reference clock down somewhere between 10mhz and 40mhz. But I am not actually trying to program an Si5351 like you are. ?Just reading some very confusing docs. ?I am curious what multiplier constraint you see an issue with. ?Getting our own Si5351 library going so we can reduce code size and smooth out any tuning disruptions for our particular application should prove valuable here. ?Especially given the constraints imposed by the Nano processor board. Jerry, KE7ER? ? ?On Wed, Apr 26, 2017 at 08:32 am, Pavel Milanes Costa wrote:
There is a multiplier constraint that when you calculate it for 25 Mhz can't reach the 900 Mhz hardcoded in my lib; that makes the PLL unlock itself. ?
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
El 26/04/17 a las 11:01, Jerry Gaffke via Groups.Io escribi¨®: According to AN619, the VCO operates between 600 and 900 MHz, regardless of the reference clock or crystal we provide. PLLA and PLLB have dividers appropriate for any reference clock between 10mhz and 100mhz to steer the VCO into the specified range, I doubt the reference clock choice affects the possible output frequencies. Hi Jerry, the 600 to 900 Mhz are suggested for the 25 to 27 Mhz range. There is a multiplier constraint that when you calculate it for 25 Mhz can't reach the 900 Mhz hardcoded in my lib; that makes the PLL unlock itself. (If I don't recall wrong it feel short for a few Mhz...) I have the math write down at home, I'm at work now. I pretend to make the max PLL VCO calculated from the supplied xtal in the init process and this multiplier. 73 de Pavel CO7WT
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
Though the Etherkit breakout board with an Si5351A has the option for a 25mhz TCXO, so it is driving an external clock into what SiLabs says is a 25-27mhz crystal oscillator. ?The C part allows you to switch between the crystal oscillator and an external reference. ?Driving what is meant to be a crystal oscillator from an external oscillator is typically allowed on this sort of part. ?I've found the Si5351 documention to be full of omissions and outright errors, it's quite possible we could drive the Si5351A with an external clock between 10 and 100 mhz in spite of what the datasheet suggests. ?Maybe they went cheap on reviewing the documentation for a part they sell for $1, the higher end parts such as the Si5338 are more thoroughly described and much of that material applies to the Si5351. Would not be surprising if they inverted the Si5351 drive level bits as you have found to be the case. Jerry, KE7ER
On Wed, Apr 26, 2017 at 08:01 am, Jerry Gaffke wrote: However, the datasheet does say that only the Si5351C has provision for the external reference clock ?
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Re: Using hot glue around supplied mic - good idea, stupid idea?
I think I must have the "kids" hot glue system as it delivered "not too hot" glue which was encouraging until I realized the viscosity was very low. As a consequence have glue within the cap but not quite where I wanted it! However, I did apply a little super glue around the mic and switch to set them into the opening before applying the hot glue. With the strain relief it all seems good enough for the time being. As I want to take the Bitx40 and mic out on a SOTA activation (www.w6png.wordpress.com) what I ended up with seems fine. Thanks for all the comments, guidance and suggestions. Paul? 
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
According to AN619, the VCO operates between 600 and 900 MHz, regardless of the reference clock or crystal we provide. ?PLLA and PLLB have dividers appropriate for any reference clock between 10mhz and 100mhz to steer the VCO into the specified range, I doubt the reference clock choice affects the possible output frequencies. However, the datasheet does say that only the Si5351C has provision for the external reference clock, the Si5351C is in a 20 pin QFN package and is way way expensive (around $10 USD), so I doubt anybody on this forum would consider using it. ?;-) ? ?As far as I know everybody here is using the $1 USD Si5351A in the 10 pin MSOP, which is restricted to using a reference crystal between 25 and 27 MHz.? Jerry, KE7ER
On Wed, Apr 26, 2017 at 07:30 am, Pavel Milanes Costa wrote: That's taking into account that if lower than 25 Mhz the max freq output will be reduced (as max PLL VPC freq will be limited) and if greater than 27 Mhz you will need to trigger tome internal division bits to get it at the end in the 25 to 27 Mhz...
?
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
El 26/04/17 a las 10:17, Jerry Gaffke via Groups.Io escribi¨®:
All Raduinos built by hfsigs have a 25mhz crystal:
Some people are using other Si5351 based breakout boards:
There's probably others. The first two above have a 25 mhz crystal, the third has a 27mhz crystal
Many thanks for the explanation Jerry, very complete reference for my goal. The Si5351 datasheet says the crystal should be be between 25 and 27mhz.
That's why I will make the Max value of the PLL VCO of the lib dependent on the xtal you use, I found a few 26.134 Mhz Xtals in my junk box I will try to test the new lib. The datasheet also says you could use an external reference clock of anything between 10 and 100 mhz.
That's taking into account that if lower than 25 Mhz the max freq output will be reduced (as max PLL VPC freq will be limited) and if greater than 27 Mhz you will need to trigger tome internal division bits to get it at the end in the 25 to 27 Mhz... I will kep it simple and assume a xtal is on the 24 to 30 Mhz and launch and make it not working beyond that limit. (I have a few 24 & 28 Mhz xtals to test that) Many TCXO's and and lab quality reference oscillators operate at 10 mhz.
I suggest you allow the user to specify the reference clock frequency at initialization to be anywhere between 10 and 100mhz.
That's my intention, by default 27 Mhz and if you user a different xtal then you have to pass it on the init function.
Jerry, KE7ER
Cheers Pavel CO7WT.
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Re: Interesting observation of the power levels of the Si5351A, reversed?
Thanks Pavel. fascinating.
Maybe the two bits is linked to an attenuator ? higher the number lesser
the output.
In such a chip an attenuator makes more sense in design!
Raj
At 26-04-2017, you wrote:
toggle quoted message
Show quoted text
Hi,
Last night while working with the Si5351a I noted something interesting,
that made me recheck the spec sheet several times:
At least in my Si5351a the power level are inverted!
In the App Note (AN619) they say clearly and I quote:
=============%<==============================
CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength
Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
=============%<==============================
In english: the least to significant bits of that register controls
power, you write a number to it and get a different power level like
this:
0 > 2 mA
1 > 4 mA
2 > 6 mA
3 > 8 mA
But I measured and checked the code it TWICE! (and more times
also).
And the power level I get by using this is exactly
REVERSED, that's:
3 > 2 mA
2 > 4 mA
1 > 6 mA
0 > 8 mA
That can be related to the reports on the birdie, and the fact that when
you "increase the power" the birdie disappears...
If the App Note is wrong, like I have tested, then they are
"decreasing the power" and then it make more sense that the
birdie gone away.
I haven't checked other Si5351a for this defect (it's unlikely that all
my Si5351 are from different lots, so all must behave the same) and also
not checked other's libs code to see if they are doing it like the AN or
if they found also this.
I repeat, this is an observation from my side that is interesting...
Can anyone out there measure your Si5351a for power levels correctness to
clear if it's an error of my Si5351a or my setup? (please report what lib
are you using)
73 de Pavel CO7WT.
PS: As some of my friends say:
The mind work like a parachute: "it works better when is
opened"
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Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
All Raduinos built by hfsigs have a 25mhz crystal: ? Some people are using other Si5351 based breakout boards: ? ?? ? ?? ? ?? There's probably others. ? The first two above have a 25 mhz crystal, the third has a 27mhz crystal The Si5351 datasheet says the crystal should be be between 25 and 27mhz. The datasheet also says you could use an external reference clock of anything between 10 and 100 mhz. ? Many TCXO's and and lab quality reference oscillators operate at 10 mhz.? I suggest you allow the user to specify the reference clock frequency at initialization to be anywhere between 10 and 100mhz. Jerry, KE7ER
On Wed, Apr 26, 2017 at 06:54 am, Pavel Milanes Costa wrote:
Tests shows that it's a problem with the lib, I assumed that the lib works with a 27 Mhz xtal, raduino uses 25 Mhz and the internal max PLL VCO is way beyond the range of the max with a 25 Mhz xtal, the the PLLs VCO are unlocked and output is disabled internally.
I wrongly used 27 Mhz in my early tests, that's why it don't worked in latest tests, when I was using a 25 Mhz xtal.
I will update the lib to work with any xtal you pass to it withing specified range (Max PLL VCO will be dynamic)
A question for the group:
The 25 Mhz xtal is the standard for the raduino?
There are raduinos out there with 27 Mhz XTALs?
?
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Interesting observation of the power levels of the Si5351A, reversed?
Hi,
Last night while working with the Si5351a I noted something
interesting, that made me recheck the spec sheet several times:
At least in my Si5351a the power level are inverted!
In the App Note (AN619) they say clearly and I quote:
=============%<==============================
CLK0_IDRV[1:0] CLK0 Output Rise and Fall time / Drive Strength
Control.
00: 2 mA
01: 4 mA
10: 6 mA
11: 8 mA
=============%<==============================
In english: the least to significant bits of that register
controls power, you write a number to it and get a different power
level like this:
0 > 2 mA
1 > 4 mA
2 > 6 mA
3 > 8 mA
But I measured and checked the code it TWICE! (and more times
also).
And the power level I get by using this is exactly
REVERSED, that's:
3 > 2 mA
2 > 4 mA
1 > 6 mA
0 > 8 mA
That can be related to the reports on the birdie, and the fact
that when you "increase the power" the birdie disappears...
If the App Note is wrong, like I have tested, then they are
"decreasing the power" and then it make more sense that the birdie
gone away.
I haven't checked other Si5351a for this defect (it's unlikely
that all my Si5351 are from different lots, so all must behave the
same) and also not checked other's libs code to see if they are
doing it like the AN or if they found also this.
I repeat, this is an observation from my side that is
interesting...
Can anyone out there measure your Si5351a for power levels
correctness to clear if it's an error of my Si5351a or my setup?
(please report what lib are you using)
73 de Pavel CO7WT.
PS: As some of my friends say:
The mind work like a parachute: "it works better when is opened"
|
Re: UPDATED bitx40mcu, bitx40 sketch using the Si5351mcu lib.
Hi,
Tests shows that it's a problem with the lib, I assumed that the lib works with a 27 Mhz xtal, raduino uses 25 Mhz and the internal max PLL VCO is way beyond the range of the max with a 25 Mhz xtal, the the PLLs VCO are unlocked and output is disabled internally.
I wrongly used 27 Mhz in my early tests, that's why it don't worked in latest tests, when I was using a 25 Mhz xtal.
I will update the lib to work with any xtal you pass to it withing specified range (Max PLL VCO will be dynamic)
A question for the group:
The 25 Mhz xtal is the standard for the raduino?
There are raduinos out there with 27 Mhz XTALs?
73 de Pavel CO7WT
toggle quoted message
Show quoted text
El 25/04/17 a las 09:58, Pavel Milanes Costa escribi¨®: Yes, confirmed.
I put together my own randuino like setup and it's not working...
I will review it in the coming days now that I have a randuino like breadboard hardware setup.
I will try to make a hybrid sketch between my arduino-arcs and the bitx/randuino hardware, to allow randuino users to try all the features in the arduino-arcs project; time... time is the problem...
73.
El 24/04/17 a las 17:02, Allard PE1NWL escribi¨®:
Pavel,
thanks, I've just quickly tried your example sketch bitx40mcu, along with
your library Si5351mcu. It compiles OK but it doesn't work on my standard
BITX40 that uses the CLK2 from the Raduino.
It seems there is no VFO signal coming from the CLK2 output.
I haven't done any troubleshooting yet, this is just my first observation.
73, Allard PE1NWL
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Was Noob in need of some assistance. Now: [BITX20] Input antenna attenuation?
Hi,
There was a reason why I advised you to use the set-up (see below) when using your sig-gen as a signal source to test the receive of your Bitx. Yes, your Bitx has a noise floor of around -120dBm and how much signal do you want to ram down its throat ?? Mabey your sig-gen doesn't go down low enough to be safe coupled directly to the RX input.
So for a quick and dirty test with low chance of doing damage it is better to just run an unshielded insulated wire from the output of your sig-gen and drape it near the Bitx board and do not connect it directly to the input connector. If your Bitx is working it should be able to hear the signal from your sig-gen.
You said in an earlier post that you can hear static, so it sounds like your Bitx is receiving something??
What level should you set sig-gen to. I would start with -100dBm. If that doesn't work you can increase the output by 10dB. As long as it is not directly connected to your RF input it should be safe.
If you do want to make a direct connection -110dBm should be about 10dB above the noise floor and should be safe but see my comments above about checking the level coming out of your sig-gen.
As I said in my last post if you don't get any response at the RX RF frequency then try tuning your sig-gen to the IF, again using the loose wire draped across the Bitx board and see if the Bitx picks-up the IF frequency.
again good luck,
Peter VK1XP
toggle quoted message
Show quoted text
-------- Original Message -------- Subject: Re: [BITX20] Noob in need of some assistance. Date: 24-04-2017 14:35 From: pierre@... To: [email protected]Hi, You can hear static. OK You got the sig gen ?? Hang a piece of wire off the output of your sig gen, then drape it near to your Bitx. Then set the sig gen to (say) 7.10MHz and tune around with your Bitx and see if you can hear the sig gen. If nothing heard then tune around with the sig gen (leave your Bitx set on mid band) and see where your Bitx is listening. Good luck, Peter VK1XP On 24-04-2017 13:49, stronggeek30s@... wrote: So I am in need of a little assistance. I'm near Portland Oregon. I
got my bitx40 v3 (c) kit. And assembled it. I don't seem to receive
anything. I have an antenna and a semi clean psu. It seems to tune and
volume seems to work. Nothing seems to come through. :-( just alot of
static
Anybody in the area that might be willing to hop of a specific freq at
a specific time and ramble a bit so I can know if I'm just doing
something silly? Lol listening to static all day is no fun :-(
Don't have my licence yet so I wasn't going to hook up the mic, PA or
ptt. A quick look at the schematic didn't seem to show any of those
three required to receive.
I'm feeding it 12.1vdc and limiting the psu to 0.250 amps (current
draw is about 0.172 amps) do those figures sound correct? Or Atleast
in an acceptable range?
Is it normal behaviour for the tuner to have to catch up towards the
limits of the tuning pot? Tried replacing said pot with a bourns 10
turn 100k pot and a 10 turn 10k pot. Same issue small tuning change
then I hit the limit of the pot then it tunes rapidly without touching
it till it hits Max freq.
Test gear on hand is a korad psu, fluke 289 dmm, mhs5200a sig gen, and
a siglent sds1102 oscope
Links:
------
[1] /g/BITX20/message/25479
[2] /mt/4963903?uid=236039
[3] /g/BITX20/post
[4] /g/BITX20/editsub?uid=236039
[5] /g/BITX20
[6] /static/tos
[7] /g/BITX20/leave/defanged
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Re: Input antenna attenuation?
-73 dbm is S9 signal, so go a lot lower than that.
73
Ken VA3ABN
On Wed, Apr 26, 2017 at 8:52 AM, <stronggeek30s@...> wrote: Having a reception issue. I was wandering what voltage/power I could dump into the antenna bnc port safely. Ie I want to inject a 7.1mhz tone into a bitx40 to trace the signal around the board.?
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Input antenna attenuation?
Having a reception issue. I was wandering what voltage/power I could dump into the antenna bnc port safely. Ie I want to inject a 7.1mhz tone into a bitx40 to trace the signal around the board.?
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Glad you like it, but credits should really go to Jerry KE7ER for the flutter fix, Jack W8TEE for improving the display routine, and many others who gave useful suggestions for?other improvements!
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Thanks Jack, I will give it a try tonight, The updating only after a 10 % drop is a great idea.
73 ON2AAV Luke
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Thanks again Allard.
I wired up a pushbutton, then reduced my drive to 2 mA and the birdie disappeared. Tuning is steady and all is working well.?
73s John VK2VOL
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On 26 Apr 2017, at 1:10 pm, Willy < W1LY@...> wrote:
Allard, I can not thank you enough for your work on v 1.07. Drive levels of 2 mA and 8 mA have,for my ears ,eliminated the 7.199 birdie. v 1.07 has also eliminated the frequency instability which was causing FMing, and the tuning system is very comfortable. Tonight I have worked South Africa,Crete,Scotland,and France with an inverted V and 5 watts from Rhode Island. I am enjoying my BitX40 thanks in large part to you. Thanks again, Willy W1LY?
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Paul Gacek (W6PNG/M0SNA)
Raj vu2zap
Allard PE1NWL
ON2AAV