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Pavel, I haven't tried coding for the Si5351, you could be right. ?However, on page 3 of AN619: 3.2. Feedback Multisynth Divider Equations ? ? ? ?fvco = fxtal * (a * b/c) where ? ?a+b/c ? ?"has a valid range of 15 + 0/1,048,575 and 90 +0/1,048,575" How the multisynth dividers get described is one of my primary issues with the Si5351 docs. ? I read that to mean ?a+b/c can take on pretty much any fractional value between 15.0 and 90.0. ?I looked over some of the other Si5351 libraries available a couple years ago and concluded that the Si5351 doc did not adequately describe the the multsynth dividers. ?However, a+b/c can take on non-integer values, with the fractional part having a resolution down to one part in a million. ?It is not just a simple divider. ? As the Si5338 docs describe, this is done by having a tapped delay line that follows a divider jumping between two adjacent integer values, some math is done for each outgoing clock edge to determine the optimum delay line setting to minimize jitter for that particular edge. Since Etherkit is successfully using an external 25mhz TCXO, I suspect fxtal on an Si5351A could successfully be driven by an external oscillator with anything between 10mhz and 40mhz as suggested at the top of page 3 of AN619. ?At 10mhz the required range for a+b/c would be between 600/10 = 60.0 and 900/10=90.0. ?At 40mhz, the required range for a+b/c would be between 600/40= 15.0 and 900/40 = 22.5. ? ?That agrees nicely with the range of 15.0 and 90.0 stated previously for a+b/c. ?If using a crystal, it must be between 25 and 27mhz just to make sure the internal oscillator starts up properly. ?If using the external clock pin on the Si5351C (that expensive 20 pin QFN), you can have an external clock of up to 100mhz, using CLKIN_DIV to bring the reference clock down somewhere between 10mhz and 40mhz. But I am not actually trying to program an Si5351 like you are. ?Just reading some very confusing docs. ?I am curious what multiplier constraint you see an issue with. ?Getting our own Si5351 library going so we can reduce code size and smooth out any tuning disruptions for our particular application should prove valuable here. ?Especially given the constraints imposed by the Nano processor board. Jerry, KE7ER? ? ?On Wed, Apr 26, 2017 at 08:32 am, Pavel Milanes Costa wrote: There is a multiplier constraint that when you calculate it for 25 Mhz can't reach the 900 Mhz hardcoded in my lib; that makes the PLL unlock itself. ? |
