It looks like while either of the 2816's /CE or /OE lines are high, the U4a gate output is low and the /OE for U3 (d0-d7) is enabled, and when the 2816's /CE AND /OE go low (read EEPROM) the U4a gate output goes high, releasing U3's /OE, and drives the U4b gate output low, selecting the U1 (a01-a7) /OE pin until the read cycle is finished.
If that is right and those need swapping, might still have to give the Pico the actual read cycle req. so it can latch that addr before the 244's swap, otherwise it will look at what it considers the addr inputs "many times" during a single read event..and possibly retreive/present the wrong data?......
A second set of eyes certainly helps, thanks for reviewing it!
Actually the output from U4a goes ... NOWHERE! That thing that looks
like a wire is a BUS and PlugRd is just one signal in the bus, but
it's not connected anywhere.
The same thing for U4b's inputs BufDirIn comes from the bus, but it is
not driven from ANYWHERE!
The intent is that U3A generates a read request to the processor which
causes an interrupt. The processor sets BufDirIn low, disabling U1
(the address buffer) and enabling U3 (the data buffer). Once it has
done that it changes GPIO8-GPIO15 from input mode to output mode.
I'll fix it and post a new schematic.
73's Skip WB6YMH
