@ Skip
Just had a bit of time to take a look at your schematic. That's a lot of work and a colossal effort to maitain legacy functions...a labor of love for sure.
I've made a bit more discovery on the codeplug PL data management...it is going to be a task to say the least to edit the PL data outside the RSS and maintain RSS compatibility. Hex editing codeplugs made by RSS? is doable but not a straight forward/valid option for many.
........More investigation needed.
Anyway, to the schematic. Am I seeing it right? It looks like U3 and U4 /OE lines should be swapped?
First, this is? presuming PlugRd = BufDirIn
If not, then disregard the following and color me lost...lol
It looks like while either of the 2816's /CE or /OE lines are high, the U4a gate output is low and the /OE for U3 (d0-d7) is enabled, and when the 2816's /CE AND /OE go low (read EEPROM) the U4a gate output goes high, releasing U3's /OE, and drives the U4b gate output low, selecting the U1 (a01-a7) /OE pin until the read cycle is finished.
If that is right and those need swapping, might still have to give the Pico the actual read cycle req. so it can latch that addr before the 244's swap, otherwise it will look at what it considers the addr inputs "many times" during a single read event..and possibly retreive/present the wrong data?......
I'm thinking all the addr lines 244s should be enabled at the same time for a valid addr read by the Pico, then swap out the lower addrs lines and swap in the data lines for the final step of the read cycle.
Also, I'm presuming that there is enough propagation delay in U4 to allow for the Hitachi's addr lines "settling time" so the Pico can get a valid addr read before the 244s swap to present the correct data on the data out port. I guess one could put the extra gate inline to add a bit more delay if needed and if so it would be enough.
I have just perused the schematic, and this is all "mental/virtual/theoretical logic".
I have not looked up settling time, propagation delay(s), or breadboarded anything with a logic analyzer.
Those SMT are going to be the death of me...lol
?If I read the .pdf right, the pitch is right at 2:1 for SOIC and 4:1 for SSOP over thru hole.
I'm going to have to get me a stack of BoBs and some cheap SOIC/TSOP/SSOP's to practice on.
The new chip tech aint making it easy for us old farts with diminished vision to play anymore.? Sign of the times....
