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Hello Softrock Fans !

Unfortunately the Kits are sold out. I will give it a try to build
mine from scratch.

I have all the parts, but not the TI OPA2228 UA. Not that easy to
access here in Europe.

1) Has anyone experiences with the performance of NE5532(A) or LT1037
? That are the replaced chips i found in the OPA2228UA-Datasheet.

2) Maybe you know more to replace with ?!

Thanks for your help !

73 de Oliver, DL6KBG DRESDEN SAXONY








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Hello Softrock Fans !
Unfortunately the Kits are sold out. I will give it a try to build
mine from scratch.
I have all the parts, but not the TI OPA2228 UA. Not that easy to
access here in Europe.

The 74hc74 is made to divide by two by connecting it's /Q output to
the data pin. in turn the Q output becomes the clock for the next
stage. This has the inherent problem that the second counter doesn't
get a clock until the first stage has changed it's output, hence the
name "ripple". It has the following sequence

Clock arrives at FF 1
delay1
Q1 flips which clocks flip flop 2 if in the right direction
delay2
Q2 changes if flip flop 1 changed in the right direction

There is a skew built into the whole arrangement, that delay2 between
Q1 flipping and Q2 flipping

A 74HC109 JK flip flop works different, it has two inputs, J and K,
the clock that clocks flip flop 1 also clocks flip flop 2 and 3 ....
N, there is no delay 2

Clock arrive
delay
Q1 Flips, Q2 Flips if needed, Q3 Flips if needed....Qn flip if needed.

In a "synchronous" counter all the Q output that need to change,
change simultaneously minimizing the delay between outputs, ergo you
can go to a higher frequency and the clocks will stay in phase.

You should use JK flip flops instead of synchronous binary counters
(a bunch of JK's inside one package) you get the same result, but
synchronous counters chips tend to be slower parts.

Here is a couple of links about it.

< >
< >
< >
< >


At 03:13 PM 10/13/2005, KY1K wrote:

Hi Oliver,

Did some more digging in the archives here. I found a message from
KD5NWA <kd5nwa@...>, who suggested the timing could be improved
with the use of a 74AC109 JK flip flop because it's synchronously
clocked, rather than a ripple counter.

I can't say whether the information is correct or not, but the timing
becomes very critical as one moves higher in frequency, so anyone
trying to push a softrock past 40 meters should consider using the JK
flip flop.

Here's the excerpt from his post to the QRP-L mailing list. Drop me a
line if you want the entire message.

---------------------------------------

KD5NWA <kd5nwa@...>

On item 4, looking at the schematic the 74ac74 dual flip flop is
implementing a asynchronous ripple counter,as such there is a built
in delay between the outputs. The second stage does get a clock
signal until the first stage output has changed. Also because they
sequenced then the variations in propagation delay adds to the
second stage delay and gives you a larger variation in timing. The
way to minimize the timing is to make a synchronous counter using a
74ac109 JK flip flop instead of a D flip flop, in that case both
flip flops are clocked simultaneously and the output also change
simultaneously. The variation in the timing is the worst variation
of the two instead of the sum of the two.

----------------------------------------

Also, if you can wait for awhile before getting the DDS, you might be
interested in the 9958 instead of the 9950. It has much better
performance, much lower spur output, can work at higher frequencies
and uses much less power. It produces 2 outputs, which can be fine
tuned provide 90 degrees phase variance, which enables higher receive
frequencies and simplifies the receiver even more.

It's big brother, the AD9999 can produce 4 outputs, each output is
tweakable...which might interest some.

I know KK7P is going to release a dual 9854 DDS sometime soon, but I
know of no one who is working on the improved 9958 design.

I'd sure like to have a 9958 based DDS!

Regards,

Art







Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ...






Yahoo! Groups Links

The 74HC74 is a synchronous dividor, NOT a ripple counter. If
the /Q was connected to the clock of the next
stage, it would be a ripple counter. Changing the D input does not
change the output until the next clock
pulse(assuming the delay in the 1st stage is less than the clock
time). The max frequency is limited by this
delay, but it does not cause skew.

Dave - WB6DHW

The 74hc74 is made to divide by two by connecting it's /Q output to
the data pin. in turn the Q output becomes the clock for the next
stage. This has the inherent problem that the second counter doesn't

get a clock until the first stage has changed it's output, hence the

name "ripple". It has the following sequence

Clock arrives at FF 1
delay1
Q1 flips which clocks flip flop 2 if in the right direction delay2
Q2 changes if flip flop 1 changed in the right direction

There is a skew built into the whole arrangement, that delay2
between Q1 flipping and Q2 flipping

A 74HC109 JK flip flop works different, it has two inputs, J and K,
the clock that clocks flip flop 1 also clocks flip flop 2 and 3 ....

N, there is no delay 2

Clock arrive
delay
Q1 Flips, Q2 Flips if needed, Q3 Flips if needed....Qn flip if
needed.

In a "synchronous" counter all the Q output that need to change,
change simultaneously minimizing the delay between outputs, ergo you

can go to a higher frequency and the clocks will stay in phase.

You should use JK flip flops instead of synchronous binary counters
(a bunch of JK's inside one package) you get the same result, but
synchronous counters chips tend to be slower parts.

Here is a couple of links about it.

< > <
>
<

tml >

< >


At 03:13 PM 10/13/2005, KY1K wrote:

Hi Oliver,

Did some more digging in the archives here. I found a message from
KD5NWA <kd5nwa@...>, who suggested the timing could be improved

with the use of a 74AC109 JK flip flop because it's synchronously
clocked, rather than a ripple counter.

I can't say whether the information is correct or not, but the
timing becomes very critical as one moves higher in frequency, so
anyone trying to push a softrock past 40 meters should consider
using the JK flip flop.

Here's the excerpt from his post to the QRP-L mailing list. Drop me

a line if you want the entire message.

---------------------------------------

KD5NWA <kd5nwa@...>

On item 4, looking at the schematic the 74ac74 dual flip flop is
implementing a asynchronous ripple counter,as such there is a
built in delay between the outputs. The second stage does get a
clock signal until the first stage output has changed. Also
because they sequenced then the variations in propagation delay
adds to the second stage delay and gives you a larger variation
in timing. The way to minimize the timing is to make a
synchronous counter using a 74ac109 JK flip flop instead of a D
flip flop, in that case both flip flops are clocked
simultaneously and the output also change simultaneously. The
variation in the timing is the worst variation of the two instead

of the sum of the two.

----------------------------------------

Also, if you can wait for awhile before getting the DDS, you might
be interested in the 9958 instead of the 9950. It has much better
performance, much lower spur output, can work at higher frequencies

and uses much less power. It produces 2 outputs, which can be fine
tuned provide 90 degrees phase variance, which enables higher
receive frequencies and simplifies the receiver even more.

It's big brother, the AD9999 can produce 4 outputs, each output is
tweakable...which might interest some.

I know KK7P is going to release a dual 9854 DDS sometime soon, but
I know of no one who is working on the improved 9958 design.

I'd sure like to have a 9958 based DDS!

Regards,

Art







Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the

same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time

...






Yahoo! Groups Links

Yahoo! Groups Links










--
No virus found in this incoming message.
Checked by AVG Anti-Virus.
Version: 7.0.344 / Virus Database: 267.12.0/132 - Release Date:
10/13/2005

-----Original Message-----
From: softrock40@... [mailto:softrock40@...] On
Behalf Of KD5NWA
Sent: Thursday, October 13, 2005 9:29 PM
To: softrock40@...
Cc: softrock40@...
Subject: Re: [softrock40] Re: Replacement for OPA2228UA


Are you sure you know what a ripple counter is? A ripple counter is
made up of multiple D Flip Flops coupled one to the next. Both ripple
and synchronous counters use edge triggered flip flops but of different
kind.

Dave,
A synchronous counter and ripple counter can be made from exactly the
same flip-flop. The difference is that in a synchronous counter the
clocks of all flip-flops are tied together and driven by the same clock
source.

The 74hc74 is two D Flip Flop, a very useful device but very
difficult to implement anything but ripple counters with it when you
need anything but divide by two. Take a look at the specification
sheet and internal diagram of a ripple counter chip, there is nothing
in there but D Flip Flops.

Dave,
The above just simply is not true, the 74hc74 makes a fine synchronous
counter, you just have to connect it correctly.


Take a look the specs of a synchronous
counter, what do you have inside, multiple JK flip flops and "and
gates" if you have more than two stages.

Dave,
Again the above ain't necessarily so.


I put several references some explain why D Flip Flops are not
useful for high speed counters that have outputs that need to be
synchronized.

Dave,
Your references are amateurs (not professionals) and are full of wheats
(Barbara Strisand).


The Q or /Q has to be connected to the next stage to implement a
binary divide by 4 counter which is the subject of the discussion so
we can generate Quadrature signals. It is synchronous only when all
you want is divide by 2 once you try to past that then you have a
ripple counter.

To create a Digital Quadrature clock requires 2 clocks one 1/2 the
frequency of the other each with exactly 50% duty cycle and
synchronized to one another. That rules out a oscillator with a
divide by two stage, the built in clock skew will make high frequency
use difficult, specially if the oscillator operates over a wide range
of frequencies.

Dave,
Again the above just ain't so. In a synchronous counter a single clock
is required. It is exactly the clock skew that makes synchronous design
a highly desirable way to do it.


Since crystal oscillators generally don't put out a signal with a
perfect 50% duty cycle and another divide by two would cause clock
skew, the way that is the easiest is to have a clock at 4X and by
using a synchronous divide by 4 counter you can have signals that
keep their phase relationship to very high frequencies, much higher
than what two 74HC74 flip flops are capable off.

Dave,
It is exactly because the crystal oscillator is not necessarily
symmetrical that the synchronous counter is the preferred method. All
flip-flops clock on the same edge and the opposite edge is not used in
the circuit for any purpose.


You can create a beautiful Quadrature clock with D flip flops and 2X
clocks if you have a commercial oscillator module that has perfect
50%(they do it by having a divide by two circuit inside) duty cycle
with three D flip flops and several 74HC86 xor gates to act as a
clock doubler and delay to clock two of the flip flops to
re-synchronize the clock signals. You can do the same thing with JK
flip flops but you only need 2 flip flops.

Dave,
The way to make a perfectly symmetrical four (4) phase clock for this
purpose is a ring counter topology. The output of each flip-flop is
connected to one switch in the Tayloe modulator/demodulator. The ring
counter is made from two dual flip-flops, the 74hc74 would be a
perfectly good choice. The steering logic around the flip-flops is a
single gate. I think a 74hc20 would do the trick. A power on reset
circuit would be desirable but not necessary.

For the frequency range that most of you are interested in I think I
could build the clock source with an Atmel processor with four output
pins. Might even be more cost effective.

The design of synchronous logic is a whole design philosophy of it's own
but once you have used it a whole lot of problems go away. I have
designed some large synchronous clock designs and with more than 1500
flip-flips. The simulator for the chip used a similar number of 74hc00
flip-flops. This work was in the early 1970s. Not a J-K flip-flop in the
entire chip.

Cash KD5SSJ


At 10:00 PM 10/13/2005, brainerd@... wrote:

The 74HC74 is a synchronous dividor, NOT a ripple counter. If
the /Q was connected to the clock of the next
stage, it would be a ripple counter. Changing the D input does not
change the output until the next clock
pulse(assuming the delay in the 1st stage is less than the clock
time). The max frequency is limited by this
delay, but it does not cause skew.

Dave - WB6DHW

The 74hc74 is made to divide by two by connecting it's /Q output to
the data pin. in turn the Q output becomes the clock for the next
stage. This has the inherent problem that the second counter doesn't

get a clock until the first stage has changed it's output, hence the

name "ripple". It has the following sequence

Clock arrives at FF 1
delay1
Q1 flips which clocks flip flop 2 if in the right direction delay2
Q2 changes if flip flop 1 changed in the right direction

There is a skew built into the whole arrangement, that delay2
between Q1 flipping and Q2 flipping

A 74HC109 JK flip flop works different, it has two inputs, J and K,
the clock that clocks flip flop 1 also clocks flip flop 2 and 3 ....

N, there is no delay 2

Clock arrive
delay
Q1 Flips, Q2 Flips if needed, Q3 Flips if needed....Qn flip if
needed.

In a "synchronous" counter all the Q output that need to change,
change simultaneously minimizing the delay between outputs, ergo you

can go to a higher frequency and the clocks will stay in phase.

You should use JK flip flops instead of synchronous binary counters
(a bunch of JK's inside one package) you get the same result, but
synchronous counters chips tend to be slower parts.

Here is a couple of links about it.

< > <
>
<

tml >

< >


At 03:13 PM 10/13/2005, KY1K wrote:

Hi Oliver,

Did some more digging in the archives here. I found a message from
KD5NWA <kd5nwa@...>, who suggested the timing could be improved

with the use of a 74AC109 JK flip flop because it's synchronously
clocked, rather than a ripple counter.

I can't say whether the information is correct or not, but the
timing becomes very critical as one moves higher in frequency, so
anyone trying to push a softrock past 40 meters should consider
using the JK flip flop.

Here's the excerpt from his post to the QRP-L mailing list. Drop me

a line if you want the entire message.

---------------------------------------

KD5NWA <kd5nwa@...>

On item 4, looking at the schematic the 74ac74 dual flip flop is
implementing a asynchronous ripple counter,as such there is a
built in delay between the outputs. The second stage does get a
clock signal until the first stage output has changed. Also
because they sequenced then the variations in propagation delay
adds to the second stage delay and gives you a larger variation
in timing. The way to minimize the timing is to make a
synchronous counter using a 74ac109 JK flip flop instead of a D
flip flop, in that case both flip flops are clocked
simultaneously and the output also change simultaneously. The
variation in the timing is the worst variation of the two instead

of the sum of the two.

----------------------------------------

Also, if you can wait for awhile before getting the DDS, you might
be interested in the 9958 instead of the 9950. It has much better
performance, much lower spur output, can work at higher frequencies

and uses much less power. It produces 2 outputs, which can be fine
tuned provide 90 degrees phase variance, which enables higher
receive frequencies and simplifies the receiver even more.

It's big brother, the AD9999 can produce 4 outputs, each output is
tweakable...which might interest some.

I know KK7P is going to release a dual 9854 DDS sometime soon, but
I know of no one who is working on the improved 9958 design.

I'd sure like to have a 9958 based DDS!

Regards,

Art







Yahoo! Groups Links

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the

same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time

...






Yahoo! Groups Links

Yahoo! Groups Links










--
No virus found in this incoming message.
Checked by AVG Anti-Virus.
Version: 7.0.344 / Virus Database: 267.12.0/132 - Release Date:
10/13/2005

Cecil Bayona
KD5NWA
www.qrpradio.com

I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ...






Yahoo! Groups Links













Yahoo! Groups Links