The 74HC74 is a synchronous dividor, NOT a ripple counter. If the /Q was connected to the clock of the next
stage, it would be a ripple counter. Changing the D input does not change the output until the next clock
pulse(assuming the delay in the 1st stage is less than the clock time). The max frequency is limited by this
delay, but it does not cause skew.
Dave - WB6DHW
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The 74hc74 is made to divide by two by connecting it's /Q output to
the data pin. in turn the Q output becomes the clock for the next
stage. This has the inherent problem that the second counter doesn't
get a clock until the first stage has changed it's output, hence the
name "ripple". It has the following sequence
Clock arrives at FF 1
delay1
Q1 flips which clocks flip flop 2 if in the right direction
delay2
Q2 changes if flip flop 1 changed in the right direction
There is a skew built into the whole arrangement, that delay2 between
Q1 flipping and Q2 flipping
A 74HC109 JK flip flop works different, it has two inputs, J and K,
the clock that clocks flip flop 1 also clocks flip flop 2 and 3 ....
N, there is no delay 2
Clock arrive
delay
Q1 Flips, Q2 Flips if needed, Q3 Flips if needed....Qn flip if needed.
In a "synchronous" counter all the Q output that need to change,
change simultaneously minimizing the delay between outputs, ergo you
can go to a higher frequency and the clocks will stay in phase.
You should use JK flip flops instead of synchronous binary counters
(a bunch of JK's inside one package) you get the same result, but
synchronous counters chips tend to be slower parts.
Here is a couple of links about it.
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At 03:13 PM 10/13/2005, KY1K wrote:
Hi Oliver,
Did some more digging in the archives here. I found a message from
KD5NWA <kd5nwa@...>, who suggested the timing could be improved
with the use of a 74AC109 JK flip flop because it's synchronously
clocked, rather than a ripple counter.
I can't say whether the information is correct or not, but the timing
becomes very critical as one moves higher in frequency, so anyone
trying to push a softrock past 40 meters should consider using the JK
flip flop.
Here's the excerpt from his post to the QRP-L mailing list. Drop me a
line if you want the entire message.
---------------------------------------
KD5NWA <kd5nwa@...>
On item 4, looking at the schematic the 74ac74 dual flip flop is
implementing a asynchronous ripple counter,as such there is a built
in delay between the outputs. The second stage does get a clock
signal until the first stage output has changed. Also because they
sequenced then the variations in propagation delay adds to the
second stage delay and gives you a larger variation in timing. The
way to minimize the timing is to make a synchronous counter using a
74ac109 JK flip flop instead of a D flip flop, in that case both
flip flops are clocked simultaneously and the output also change
simultaneously. The variation in the timing is the worst variation
of the two instead of the sum of the two.
----------------------------------------
Also, if you can wait for awhile before getting the DDS, you might be
interested in the 9958 instead of the 9950. It has much better
performance, much lower spur output, can work at higher frequencies
and uses much less power. It produces 2 outputs, which can be fine
tuned provide 90 degrees phase variance, which enables higher receive
frequencies and simplifies the receiver even more.
It's big brother, the AD9999 can produce 4 outputs, each output is
tweakable...which might interest some.
I know KK7P is going to release a dual 9854 DDS sometime soon, but I
know of no one who is working on the improved 9958 design.
I'd sure like to have a 9958 based DDS!
Regards,
Art
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Cecil Bayona
KD5NWA
www.qrpradio.com
I fail to see why doing the same thing over and over and getting the
same results every time is insanity: I've almost proved it isn't;
only a few more tests now and I'm sure results will differ this time ...
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