On 29/08/2023 18:54, Jonathan Burchmore
wrote:
On Tue, Aug 29, 2023 at 09:58 AM, Kees T wrote:
You measured the right point. It just shows that the
78M33 3.3V VDD output is getting slapped around a little by
several 2.2uF Tantalums on the board vs having a couple of 47uF
Tantalums at the processor. Surprising that all those 2.2uF
Tantalums on the board are apparently able to hold the 3.3V
level for the full 250ms until the SMPS comes ON.
I don't think LIN_REG_EN is turning "off" at 80ms--I think what
we're seeing is the handoff from the initial supply voltage
(through PWR_ON?) to the 3.3v signal from the processor PD7 once
it has booted up sufficiently. ?I seem to recall Hans discussing
this in his FDIM presentation.
It seems to be in a half way state at that time, The linear
supply FET Q102 is on and so is Q110 which provides a load for the
SMPS. But Q111 is also on so the power can come from the linear or
the SMPS - or go into the SMPS and the 47R load.
Then when the SMPS pulls VDD above the 3V which the linear can
supply the SMPS takes over and LIN_REG_EN is pulled low.
Three state logic, on, half on and off.?
Chris, G5CTH
Jonathan KN6LFB
