On Tue, Aug 29, 2023 at 09:58 AM, Kees T wrote:
You measured the right point. It just shows that the 78M33 3.3V VDD output is getting slapped around a little by several 2.2uF Tantalums on the board vs having a couple of 47uF Tantalums at the processor. Surprising that all those 2.2uF Tantalums on the board are apparently able to hold the 3.3V level for the full 250ms until the SMPS comes ON.
I don't think LIN_REG_EN is turning "off" at 80ms--I think what we're seeing is the handoff from the initial supply voltage (through PWR_ON?) to the 3.3v signal from the processor PD7 once it has booted up sufficiently. ?I seem to recall Hans discussing this in his FDIM presentation.
Jonathan KN6LFB
