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Also, confirm that Pin 10 on Motherboard is the reset - maybe there are different K1000 schematics. Follow the RESET_IN wire thru the harness between boards. I would think Pin 3 should be RESET_IN on

Could be bad cable or connector soldering (cracked).. What about RESET* on the CPU pin 18 (inverted signal from RESET_IN)?? ? If always stuck high, this means CPU won't boot. RESET* needs to be

I did a quick check and got the ff: Reset (J4 pin 3) at PSU 4.97v at power up then goes to 0v Reset (J4 pin 10) at motherboard 0v at power up and stays at 0v

Also look at RESET_IN signal on scope.? It should go high (+5V) for a short time (< 500 ms) when power is switched on and go low (0V). At the CPU, RESET_IN is inverted to RESET* - an active low

Hello Joey. No, should be 2 volts because it's minimum for ls02 logic high level. Check the power board.

Thank you for your inputs. I only have time to do a quick check on U45. ?Both pin 2 and pin 8 have 1.21v. Is this the?normal voltage for these pins? ? I'll check on the other points suggested when

Joey,? Given that UART and Timer failed in diagnostic tests,? I would check POWER_OK signal as Vladimir suggests. POWER_OK can block IRQ (interrupt requests) from UART and Timer as shown in

Vladimir is correct - all clock signals should be square wave shaped (high harmonic content) for clean clock transitions. If they are sine shaped (less harmonics) that can cause issues for digital

I attach a bad signal photo)

Ok, so if you have oscilloscope check frequency form at pin 15 of the cpu. It should be square wave without stretching or shaping. If it's sine, you have problems with clock generator. At my last

Also, check for /Power OK high U045, pins 2 and 8. That line goes to CPU pins 25 and 24, interupt levels.

PAL chip used in k1000 have lock bit, maded after factory programming. It prevent to read rom or write. I try to read this chip with my gal/pal programer but unfortunetly, hex is empty.

PAL is programmable array logic - they are blank (like a ROM) and need to be programmed. You would need the original JEDEC programming bitmap file (Like a ROM hex/bin file) and a PAL programmer. Not

The OS chips are new and the?PAL chip?is much easier to replace than the CPU. ?I guess I'll try to replace that first.? Thanks for the insights. ?

K1000 schematic shows 68000 CPU is clocked at 10 MHz (20 MHz oscillator divided by 2).? ?This is 100 nanosecond clock cycle. If your scope has 20 MHz bandwidth or greater, it may be enough to

Thanks for the reply. The K1000?guide does say an oscilloscope is needed to perform some of the troubleshooting. Unfortunately, ?I only have a cheap portable?scope with?very limited

More info on bus timing: http://users.cecs.anu.edu.au/~Matthew.James/engn3213-2002/notes/busnode7.html Timing diagram below shows a bus read cycle on a 68000 CPU - at bottom is DTACK signal. Taken

DTACK is Motorola 68000 CPU signal? for Data Transfer Acknowledge.? ? It is very fast signal? - a few tens of nanoseconds in duration. To see it toggle, you would need an oscilloscope or logic

Dear all, I am going thru Chapter 5 Basic Troubleshooting of the K1000 and under letter I., it says check for DTack toggling on U017, pin 10.??It further states:?? "If this line never

Thank you for all?the helpful comments. I have removed, cleaned, and reseated all the socketed?IC's a few times with the same results. I also see no visible breaks in the PCB?traces.? Thanks for