More info on bus timing:??
Timing diagram below shows a bus read cycle on a 68000 CPU - at bottom is DTACK signal.
Taken from:??
Four clock cycles (fastest speed) shows DTACK active low (0 volts) for 1.5 cycles.? ?
With a 20 MHz CPU clock, DTACK low is 75 nanoseconds,? with 10 MHz clock DTACK low is 150 nanoseconds.
An oscilloscope with 50 MHz bandwidth or higher would be needed to see these events.
For slower speed memory or peripheral devices (e.g. UART for MIDI), the bus cycle is
extended (more clocks,? wait states) until the DTACK is asserted - indicating bus cycle is complete.
