Also, confirm that Pin 10 on Motherboard is the reset - maybe there are different K1000 schematics.
Follow the RESET_IN wire thru the harness between boards.
I would think Pin 3 should be RESET_IN on both ends of harness, but maybe Kurzweil modified the wire harness to remap pins.
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Could be bad cable or connector soldering (cracked)..
What about RESET* on the CPU pin 18 (inverted signal from RESET_IN)?? ? If always stuck high, this means CPU won't boot.
RESET* needs to be asserted low (0V) on power up and then go high (+5V)
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I did a quick check and got the ff:
Reset (J4 pin 3) at PSU 4.97v at power up then goes to 0v
Reset (J4 pin 10) at motherboard 0v at power up and stays at 0v
On Friday, February 12, 2021, 1:36 AM, mjkirk12 via groups.io <mjkirk12@...> wrote: Also look at RESET_IN signal on scope.? It should go high (+5V) for a short time (< 500 ms) when power is switched on and go low (0V).
At the CPU, RESET_IN is inverted to RESET* - an active low signal.? ?RESET* is high in normal operation.
Both RESET_IN and POWER_OK use the unregulated DC to the 7805 5 volt regulator to operate.
This circuit has several components that can be probed - could be bad transistor, zener diode or nearby component that has failed.
As a test, you could substitute a separate bench +5V supply,? Wire POWER_OK to ground and quickly pulse the reset line Low-Hi-Low with a toggle switch.
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Also look at RESET_IN signal on scope.? It should go high (+5V) for a short time (< 500 ms) when power is switched on and go low (0V).
At the CPU, RESET_IN is inverted to RESET* - an active low signal.? ?RESET* is high in normal operation.
Both RESET_IN and POWER_OK use the unregulated DC to the 7805 5 volt regulator to operate.
This circuit has several components that can be probed - could be bad transistor, zener diode or nearby component that has failed.
As a test, you could substitute a separate bench +5V supply,? Wire POWER_OK to ground and quickly pulse the reset line Low-Hi-Low with a toggle switch.
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Hello Joey. No, should be 2 volts because it's minimum for ls02 logic high level. Check the power board.
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Thank you for your inputs.
I only have time to do a quick check on U45. ?Both pin 2 and pin 8 have 1.21v. Is this the?normal voltage for these pins? ?
I'll check on the other points suggested when I get back home. ?
Thanks again for your help.
On Thursday, February 11, 2021, 10:52 PM, mjkirk12 via groups.io <mjkirk12@...> wrote: Joey,? Given that UART and Timer failed in diagnostic tests,? I would check POWER_OK signal as Vladimir suggests. POWER_OK can block IRQ (interrupt requests) from UART and Timer as shown in schematic (found on K1000.net) 
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Joey,? Given that UART and Timer failed in diagnostic tests,? I would check POWER_OK signal as Vladimir suggests. POWER_OK can block IRQ (interrupt requests) from UART and Timer as shown in schematic (found on K1000.net) 
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Vladimir is correct - all clock signals should be square wave shaped (high harmonic content) for clean clock transitions.
If they are sine shaped (less harmonics) that can cause issues for digital logic.
An oscilloscope and/or scope probes with insufficient bandwidth (< 20 MHz)? can also filter out these harmonics and show a sine shape clock as well.
A good (>100 MHz BW) scope with matching 100 MHz BW probes are needed to see the true clock shape.
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I attach a bad signal photo) 
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Ok, so if you have oscilloscope check frequency form at pin 15 of the cpu. It should be square wave without stretching or shaping. If it's sine, you have problems with clock generator. At my last repairing I observe sine wave at that pin, U38 was bad and I replaced it.
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Also, check for /Power OK high U045, pins 2 and 8. That line goes to CPU pins 25 and 24, interupt levels.
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PAL chip used in k1000 have lock bit, maded after factory programming. It prevent to read rom or write. I try to read this chip with my gal/pal programer but unfortunetly, hex is empty.
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PAL is programmable array logic - they are blank (like a ROM) and need to be programmed.
You would need the original JEDEC programming bitmap file (Like a ROM hex/bin file) and a PAL programmer.
Not sure if that is possible, unless someone read out a known good device.
PAL devices are no longer made - finding a blank one may not be easy.
I would probe the chip select signals to the timer and UART - maybe they are not responding to the CPU?
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The OS chips are new and the?PAL chip?is much easier to replace than the CPU. ?I guess I'll try to replace that first.? Thanks for the insights.
On Thursday, February 11, 2021, 12:10 AM, mjkirk12 via groups.io <mjkirk12@...> wrote: K1000 schematic shows 68000 CPU is clocked at 10 MHz (20 MHz oscillator divided by 2).? ?This is 100 nanosecond clock cycle.
If your scope has 20 MHz bandwidth or greater, it may be enough to trigger on DTACK events.
If CPU is accessing non-existent memory ("off the rails"), then DTACK signal will never pulse low.
This would imply the software (code) in the ROM chips is bad,? PAL chip is bad or CPU could be bad.
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K1000 schematic shows 68000 CPU is clocked at 10 MHz (20 MHz oscillator divided by 2).? ?This is 100 nanosecond clock cycle.
If your scope has 20 MHz bandwidth or greater, it may be enough to trigger on DTACK events.
If CPU is accessing non-existent memory ("off the rails"), then DTACK signal will never pulse low.
This would imply the software (code) in the ROM chips is bad,? PAL chip is bad or CPU could be bad.
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Thanks for the reply. The K1000?guide does say an oscilloscope is needed to perform some of the troubleshooting. Unfortunately, ?I only have a cheap portable?scope with ?very limited functions.??
On Wednesday, February 10, 2021, 11:28 PM, mjkirk12 via groups.io <mjkirk12@...> wrote: DTACK is Motorola 68000 CPU signal? for Data Transfer Acknowledge.? ? It is very fast signal? - a few tens of nanoseconds in duration.
To see it toggle, you would need an oscilloscope or logic analyzer set to edge trigger on the event.
Some info on the topic:?https://en.wikipedia.org/wiki/DTACK_Grounded
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More info on bus timing:?? Timing diagram below shows a bus read cycle on a 68000 CPU - at bottom is DTACK signal. Taken from:?? Four clock cycles (fastest speed) shows DTACK active low (0 volts) for 1.5 cycles.? ? With a 20 MHz CPU clock, DTACK low is 75 nanoseconds,? with 10 MHz clock DTACK low is 150 nanoseconds. An oscilloscope with 50 MHz bandwidth or higher would be needed to see these events. For slower speed memory or peripheral devices (e.g. UART for MIDI), the bus cycle is extended (more clocks,? wait states) until the DTACK is asserted - indicating bus cycle is complete. 
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DTACK is Motorola 68000 CPU signal? for Data Transfer Acknowledge.? ? It is very fast signal? - a few tens of nanoseconds in duration.
To see it toggle, you would need an oscilloscope or logic analyzer set to edge trigger on the event.
Some info on the topic:?https://en.wikipedia.org/wiki/DTACK_Grounded
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Dear all,
I am going thru Chapter 5 Basic Troubleshooting of the K1000 and under letter I., it says check for DTack toggling on U017, pin 10.??It further states:??
"If this line never goes low, the unit is hung in a non-existent memory access. DTack is generated by PAL (U08, pin 16)."
I'd appreciate it if someone with a working K1000 can check the voltage on U017, pin 10.??Does the voltage change from high to low and back???Basically I want to know what is the behavior of the voltage on this pin in a working K1000.??
Thanks in advance.??
On Tuesday, February 9, 2021, 6:19 PM, Joey Mastrili via groups.io <jmastrili@...> wrote:
Thank you for all?the helpful comments.
I have removed, cleaned, and reseated all the socketed?IC's a few times with the same results. I also see no visible breaks in the PCB?traces.?
Thanks for the offer to send me the?OS?files.?Unfortunately, I?have no IC programmer and cannot burn new chips. ?I'll check the traces around the ACIA chips as suggested.
On Tuesday, February 9, 2021, 2:06 AM, Vladimir <shtirlitzz11@...> wrote: Hello Joey. Could you do the dump of the new OS chips for comparing it. Or I could make the dumps of two OS chips and send you binnary) surely if you have the programer. UART and timer signals come from HD63 ACIA chips, did you check traces around those?
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Thank you for all?the helpful comments.
I have removed, cleaned, and reseated all the socketed?IC's a few times with the same results. I also see no visible breaks in the PCB?traces.?
Thanks for the offer to send me the?OS?files.?Unfortunately, I?have no IC programmer and cannot burn new chips. ?I'll check the traces around the ACIA chips as suggested.
On Tuesday, February 9, 2021, 2:06 AM, Vladimir <shtirlitzz11@...> wrote: Hello Joey. Could you do the dump of the new OS chips for comparing it. Or I could make the dumps of two OS chips and send you binnary) surely if you have the programer. UART and timer signals come from HD63 ACIA chips, did you check traces around those?
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