I'm glad to hear that you got it fixed!
On Monday, March 1, 2021, 3:36 PM, Frank D via groups.io <rhythm4_4@...> wrote: I've been following what's going on with Joey's 1000PX and hoping mine would not suffer a similar fate... Well, I finally dug back into it by first replacing all electrolytic caps in the power supply. Popped it back in and hit the power switch... Saw the top row of blocks on the display and was about to utter an expletive, when the relay clicked and the unit booted up!? Ran through the patch bank a bit and tested for sound. It works!
I also bought replacement electrolytics for the main board, so I replaced those too while I had the inspiration. Put it back together and hooked up some Midi. This one is going back into my rack.
What's the current wisdom on replacing the display or backlight? I wanted to make sure the rest of the unit worked before attacking it.
Thanks to everyone for their tips and advice!
--
peace,
Frank Dickinson
90 East Productions
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I've been following what's going on with Joey's 1000PX and hoping mine would not suffer a similar fate... Well, I finally dug back into it by first replacing all electrolytic caps in the power supply. Popped it back in and hit the power switch... Saw the top row of blocks on the display and was about to utter an expletive, when the relay clicked and the unit booted up!? Ran through the patch bank a bit and tested for sound. It works!
I also bought replacement electrolytics for the main board, so I replaced those too while I had the inspiration. Put it back together and hooked up some Midi. This one is going back into my rack.
What's the current wisdom on replacing the display or backlight? I wanted to make sure the rest of the unit worked before attacking it.
Thanks to everyone for their tips and advice!
--
peace,
Frank Dickinson
90 East Productions
|
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Where can I download this? Thanks.
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My understanding is this does not effect midi transmissions or hardware compliance. Midi1.0 is still useable. Just that any midi apps, like ObjectEditorX, will require code fixes to handle midi transmissions in OS11. So things like Emagic¡¯s Unitor and AMT8 interfaces will no longer function, for example, as they require midi drivers. But I am not an expert!!!
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On Feb 23, 2021, at 5:47 PM, Max Thompson <maxibillionthompsonmusic@...> wrote:
? Does that mean that current class compliant usb midi devices will not work on OS11? On Tue, Feb 23, 2021 at 7:05 PM David Greenwood via <fiansamusic= [email protected]> wrote:
I just learned from a fellow K1000/1200 group user last week that there are issues using ObjectEditorX with Big Sur (OS11). On doing some research I discovered that Apple have completely revised CoreMidi - first time in 20 years!! This was clearly done to encompass the new MIDI2.0 specification, but introduces no backward compatibility with OS10.
As I firmly belong in the dark ages, there is no way I am going to be able to maintain this product going forward. So after much thought I think the only solution will be to publish the source code, and let some other adventurous sole work out how to include the new CoreMidi library. So my question to the group is where should the source code reside?
Also any courageous sole willing to dive into XCode/Objective-C/CoreMidi to make it work with macOS11?
Thanks
David
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I would hold off on CPU replacement - unless there is no E clock output (1 MHz).?
Focus on U45 - are you sure you have a 74LS02? Quad NOR gate part?
If you used a different part, e.g.? 74LS08 (Quad AND gate)? - that would explain U45A and
U45B operation - but not U45C - can't understand what is going on.
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I tried it one more time?using a new IC and made sure that pins 1 and 10 are not connected or touching any other part. ?
I got the same reading (low on both pins)?which is really strange. ?I was hoping it will pulse on pin 1 and be high on pin 10 because that?narrows?down the problem to the CPU. ?
With this unusual reading, what do you think should be the next step??
Is it worth replacing the CPU at this time or continue to investigate U45??
On Wednesday, February 24, 2021, 1:08 PM, mjkirk12 via groups.io <mjkirk12@...> wrote: Yes I agree with your conclusions.? Seems as if U45 is bad again - something damaged the output drivers (pins 1 and 10)
Did you use a IC socket for U45 - swap in another IC,? leave pins 1 and 10 lifted and check again.
A dead 68000 CPU could have shorted these outputs (IPL0,1,2), causing high current drain and blowing the outputs.
This latch-up can happen if CPU is not provided a good clock input after de-asserting RESET* (reset high)
Or there is bad circuit trace shorted to ground between IC45 and CPU?? Maybe trace passes under components - hard to see.
Do you have CLK at 10MHz and E clock output at 1 MHz?
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Yes I agree with your conclusions.? Seems as if U45 is bad again - something damaged the output drivers (pins 1 and 10)
Did you use a IC socket for U45 - swap in another IC,? leave pins 1 and 10 lifted and check again.
A dead 68000 CPU could have shorted these outputs (IPL0,1,2), causing high current drain and blowing the outputs.
This latch-up can happen if CPU is not provided a good clock input after de-asserting RESET* (reset high)
Or there is bad circuit trace shorted to ground between IC45 and CPU?? Maybe trace passes under components - hard to see.
Do you have CLK at 10MHz and E clock output at 1 MHz?
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Does that mean that current class compliant usb midi devices will not work on OS11?
On Tue, Feb 23, 2021 at 7:05 PM David Greenwood via <fiansamusic= [email protected]> wrote:
I just learned from a fellow K1000/1200 group user last week that there are issues using ObjectEditorX with Big Sur (OS11). On doing some research I discovered that Apple have completely revised CoreMidi - first time in 20 years!! This was clearly done to encompass the new MIDI2.0 specification, but introduces no backward compatibility with OS10.
As I firmly belong in the dark ages, there is no way I am going to be able to maintain this product going forward. So after much thought I think the only solution will be to publish the source code, and let some other adventurous sole work out how to include the new CoreMidi library. So my question to the group is where should the source code reside?
Also any courageous sole willing to dive into XCode/Objective-C/CoreMidi to make it work with macOS11?
Thanks
David
|
I just learned from a fellow K1000/1200 group user last week that there are issues using ObjectEditorX with Big Sur (OS11). On doing some research I discovered that Apple have completely revised CoreMidi - first time in 20 years!! This was clearly done to encompass the new MIDI2.0 specification, but introduces no backward compatibility with OS10.
As I firmly belong in the dark ages, there is no way I am going to be able to maintain this product going forward. So after much thought I think the only solution will be to publish the source code, and let some other adventurous sole work out how to include the new CoreMidi library. So my question to the group is where should the source code reside?
Also any courageous sole willing to dive into XCode/Objective-C/CoreMidi to make it work with macOS11?
Thanks
David
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I lifted pins 1 and 10 from the socket and got the following readings:?
Pin 1?? ??Low??no pulse Pin 10???Low
I was?expecting pin 1 to?pulse H and L and was surprised that it remained L.
Likewise with pin 10. I was expecting it to go high (following the function table) but it remained low.?
I was also able to confirm the voltage on the following pins:
Pin 14?? ?4.96v Pin 49? ??4.96v
Joey
On Tuesday, February 23, 2021, 1:01 AM, mjkirk12 via groups.io <mjkirk12@...> wrote: Pin 17??High? ? ?Pin 18??High? ?- These are OK
Pin 23??Low? ?Pin 24??Low? ?Pin 25??Low? ?These are active low interrupts (input to CPU).
U45 C
Pin 5???pulses H and L? ??This is OK - Timer is generating periodic IRQ?
Pin 6???L? ?OK, no interrupt from UART
Pin 4???pulses H and L? ?OK
U45 A
Pin 2???L? ? ?OK - POWER_OK is low,?
Pin 3???pulses H and L? ?OK - pulsing due to Timer IRQ activity
Pin 1? ?L?? ?--->?Goes to U17 pin 24? ? BAD? - this should also be pulsing high and low,? ?Pin 24 is IPL1 interrupt input to CPU
Either the CPU is bad - pulling this low OR there is a damaged PCB trace that is shorted to ground.
U45 B
Pin 8? ??L? ?OK - POWER_OK is low
Pin 9? ??L? ?OK - no UART IRQ active
Pin 10??L?? ?--->?Goes to U17 pin 25 ??and?23? ?BAD? - this should be HIGH.? ?Pins 23 and 25 are? IPL0 and IPL2? interrupt input to CPU
Either the CPU is bad - pulling this low OR there is a damaged PCB trace that is shorted to ground between the U45 and the CPU.
Maybe try lifting pin 1 and pin 10 of U45 (disconnect from PCB) and see if these change (Pin 1 pulsing,? Pin 10 High).
Normally at boot time, the interrupts are masked (ignored) until the CPU has completed boot code execution and has entered the main application code.
Then interrupts are enabled and processed.? ? With IPL0,IPL1 and IPL2 all low, the CPU will be constantly servicing interrupts and unable to perform other tasks.
NOR gate (also called a negative AND gate) has the following operation:
Also check these other pins (need scope)
14, 49? Vdd? = +5V DC for CPU power? - having no power could pull IPL0,1,2 low
15 CLK must have a 10 MHz clock
20 E - should have clock signal at 1 MHz.? ? A single period of clock E consists of 10 MC68000 CLK periods (six low, four high).
9? R/W*? - read/write should be toggling high/low
6 AS*? - address strobe should be toggling high/low
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Vladimir,
I do not have direct experience with K1000/K1200, but in my job as engineer, this is typically how timers work - generating periodic or event triggered interrupts to the CPU.
At reset, I don't know if the K1000PX timer starts generating interrupts or it must first be programmed by the CPU during boot up.
Datasheet on the Timer chip:? ??
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Hello mjkirk12. Do I understand correctly that the timer chip during startup should generate a signal on U45 from high to low and vice versa? If this is so, then this explains a lot, I have non-working k1000 for a long time. When turned on, I observed a constantly high signal on pin 5 of U45.
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Pin 17??High? ? ?Pin 18??High? ?- These are OK
Pin 23??Low? ?Pin 24??Low? ?Pin 25??Low? ?These are active low interrupts (input to CPU).
U45 C
Pin 5???pulses H and L? ??This is OK - Timer is generating periodic IRQ?
Pin 6???L? ?OK, no interrupt from UART
Pin 4???pulses H and L? ?OK
U45 A
Pin 2???L? ? ?OK - POWER_OK is low,?
Pin 3???pulses H and L? ?OK - pulsing due to Timer IRQ activity
Pin 1? ?L?? ?--->?Goes to U17 pin 24? ? BAD? - this should also be pulsing high and low,? ?Pin 24 is IPL1 interrupt input to CPU
Either the CPU is bad - pulling this low OR there is a damaged PCB trace that is shorted to ground.
U45 B
Pin 8? ??L? ?OK - POWER_OK is low
Pin 9? ??L? ?OK - no UART IRQ active
Pin 10??L?? ?--->?Goes to U17 pin 25 ??and?23? ?BAD? - this should be HIGH.? ?Pins 23 and 25 are? IPL0 and IPL2? interrupt input to CPU
Either the CPU is bad - pulling this low OR there is a damaged PCB trace that is shorted to ground between the U45 and the CPU.
Maybe try lifting pin 1 and pin 10 of U45 (disconnect from PCB) and see if these change (Pin 1 pulsing,? Pin 10 High).
Normally at boot time, the interrupts are masked (ignored) until the CPU has completed boot code execution and has entered the main application code.
Then interrupts are enabled and processed.? ? With IPL0,IPL1 and IPL2 all low, the CPU will be constantly servicing interrupts and unable to perform other tasks.
NOR gate (also called a negative AND gate) has the following operation:
Also check these other pins (need scope)
14, 49? Vdd? = +5V DC for CPU power? - having no power could pull IPL0,1,2 low
15 CLK must have a 10 MHz clock
20 E - should have clock signal at 1 MHz.? ? A single period of clock E consists of 10 MC68000 CLK periods (six low, four high).
9? R/W*? - read/write should be toggling high/low
6 AS*? - address strobe should be toggling high/low
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I am getting the following readings on the CPU:
Pin 17??High Pin 18??High Pin 23??Low Pin 24??Low Pin 25??Low
U45 C Pin 5???pulses H and L Pin 6???L Pin 4???pulses H and L
U45 A Pin 2???L Pin 3???pulses H and L Pin 1? ?L?? ?--->?Goes to U17 pin 24
U45 B Pin 8? ??L Pin 9? ??L Pin 10??L?? ?--->?Goes to U17 pin 25 ? ? ? ? ? ? ? ? ? ? ? ? ? ?and?23
I thought U45 was defective so I replaced it but I got the same readings after installing a new IC.?
Pin 5 of U45 comes from the timer IRQ.??Is it normal for the voltage to pulse from high to low and back???
Thanks for any inputs.?
Joey
On Saturday, February 20, 2021, 10:42 PM, mjkirk12 via groups.io <mjkirk12@...> wrote: Yes, these all should normally be high.
Pin 17 HALT* must be high (stops CPU when low)
Pin 18 RESET* must pulse low to reset CPU.? ?(stops CPU if held low)
Pins 23-25 should normally be high, but with interrupt event (UART/TIMER), could be low
Other pins (need scope)
14, 49? Vdd? = +5V DC for CPU power
15 CLK must have a 10 MHz clock
20 E - should have clock signal at 1 MHz.? ? A single period of clock E consists of 10 MC68000 CLK periods (six low, four high).
9? R/W*? - read/write should be toggling high/low
6 AS*? - address strobe should be toggling high/low
Most data and address bus lines should all toggle high/low as well - showing activity of CPU.
More info:
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Yes, these all should normally be high.
Pin 17 HALT* must be high (stops CPU when low)
Pin 18 RESET* must pulse low to reset CPU.? ?(stops CPU if held low)
Pins 23-25 should normally be high, but with interrupt event (UART/TIMER), could be low
Other pins (need scope)
14, 49? Vdd? = +5V DC for CPU power
15 CLK must have a 10 MHz clock
20 E - should have clock signal at 1 MHz.? ? A single period of clock E consists of 10 MC68000 CLK periods (six low, four high).
9? R/W*? - read/write should be toggling high/low
6 AS*? - address strobe should be toggling high/low
Most data and address bus lines should all toggle high/low as well - showing activity of CPU.
More info:
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Hi.?
I will try to probe?the logic circuits later today?but?would like to clarify first?if pins 17,18, 23,?24, and 25 of U17?should be high (meaning 3-5v) for the K1000 to boot??
On Saturday, February 13, 2021, 1:32 AM, mjkirk12 via groups.io <mjkirk12@...> wrote: If RESET_IN is low, then U44 (74AC05) should invert to give RESET* as high signal to CPU
Possible causes:
1) U44 not getting + 5V power
2) U44 is bad
3) Some other device wired to RESET* is shorting to ground (pulling low)
But you also said RESET_IN at connector was not changing - that needs to be repaired as well.
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If RESET_IN is low, then U44 (74AC05) should invert to give RESET* as high signal to CPU
Possible causes:
1) U44 not getting + 5V power
2) U44 is bad
3) Some other device wired to RESET* is shorting to ground (pulling low)
But you also said RESET_IN at connector was not changing - that needs to be repaired as well.
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Yes, RESET asserted low (0V) holds the processor in reset -it won't start up.
to run it needs to be high (3V to 5V).
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CPU Pin 18 is 0 volts at power up and does?not change.? Is this the reason why it doesn't boot??
On Friday, February 12, 2021, 10:39 PM, mjkirk12 via groups.io <mjkirk12@...> wrote: Could be bad cable or connector soldering (cracked)..
What about RESET* on the CPU pin 18 (inverted signal from RESET_IN)?? ? If always stuck high, this means CPU won't boot.
RESET* needs to be asserted low (0V) on power up and then go high (+5V)
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