Yes, these all should normally be high.
Pin 17 HALT* must be high (stops CPU when low)
Pin 18 RESET* must pulse low to reset CPU.? ?(stops CPU if held low)
Pins 23-25 should normally be high, but with interrupt event (UART/TIMER), could be low
Other pins (need scope)
14, 49? Vdd? = +5V DC for CPU power
15 CLK must have a 10 MHz clock
20 E - should have clock signal at 1 MHz.? ? A single period of clock E consists of 10 MC68000 CLK periods (six low, four high).
9? R/W*? - read/write should be toggling high/low
6 AS*? - address strobe should be toggling high/low
Most data and address bus lines should all toggle high/low as well - showing activity of CPU.
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