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hello all,

i just discovered this group and their efforts...
congratulations for the SA analyzer and its fantastic price.
you have killed to us the desire of design/build our own SA, hi hi

i can not find the schematic anywhere, so i will talk in reference i could see in

http://www.carnut.info/tinySA/tinySA.html
https://www.changpuak.ch/electronics/Arduino-Project-VISIONARY.php

from my point of view, the worst performance of the SA is RBW, limited by the receiver channel bandwidth.

for a communications application, during some time i have been looking "one-chip" transceiver
with a very narrow channel bandwidth. in fact I landed here to discover which chip you were using...

well, some weeks ago I found this chip:

AT86RF215M
3.03EUR@25UNITS in MOUSER
http://ww1.microchip.com/downloads/en/devicedoc/atmel-42415-wireless-at86rf215_datasheet.pdf
AT86RF215 / AT86RF215IQ / AT86RF215M
Sub-1GHz/2.4GHz Transceiver and I/Q Radio

where you can extract the zeroif IQ data stream 13+13bits with a sampling frequency of 4Msps max.

i am not sure if you need some other functionality in the SI4432 "one-chip" transceiver,
but it seems a good idea to connect AT86RF215M to a STM32F4? and, doing decimation, improve the
dynamic range and RBW (1bit more reducing 4 times the sample speed)

some devices of the STM32F family include a delta-sigma digital filter ("DS demodulator")
it is not very well documented for this purpose, but it seems possible to do decimation by hardware.

well, this is my 2cents to this nice project that it will save a lot of time to lots of people

73 from catalonia,
ea3ghs eduardo

I have done some datasheet reading on the AT86RF215M, but mostly as a solution for low cost sdr uses, not as a spectrum analyzer IF :)
The annoying bit about it is the interface via which the IQ samples flow.?
It's a 128mbps LVDS interface with a 64MHz clock as it samples on both clock edges, being DDR.
So even if the samplerate is only 4MSPs, the datarate is much higher.?
I have so far contemplated using a small FPGA or CPLD as the glue logic from it to an mcu like nxp i.mx rt crossover series or stm32f7.?
As the annoying DDR clock won't work with most SPI peripherals or other similar existing interfaces.
On the the bright side one could decimate in the FPGA, so there's that.

-Ismo

hello all,
hello ismo,

thanks for the answer.
i have no experience with LVDS buses

but i can see the numbers: 4MSaps*13bit/Sa*2channels=104Mbps
the chip evaluation board uses two SATA connectors for this high speed bus: clk+rx and clk+tx
unfortunately, i can not find this kind of interface in the now common STM32 microcontrollers.

maybe using a 3EUROs-FPGA ;-) you can merge:

1)a LVDS+DDR reception interface,
2)a cascade of CIC decimatig filters
3)the operation i*i+q*q
4)a interface with the microcontroller

the microcontroller finishes the signal processing

5)operation SQRT(x)
6)averaging (videobandwith) filter, VBW? (trick RBW=3*VBW)
7)operation log10(x) to present the information in a logarithmic scale

this solution means, at least, 3EUR plus some knowledge of verilog and current synthesis tools

==
sounds interesting, but...
i will prefer a more analog solution:
a double conversion superhetereodyne 434.2MHz receiver with a second IF in 1.2MHz
this IF can be sampled by a STM32F4xx 7Msps 12b ADCs,
with the same steps 1-7 but implemented a C program.

73 from eduardo, ea3ghs

A low cost FPGA would be my choise as well.?
I was unaware of the evaluation board, but would have used sata cables on my planed test board.?
They just are so cheap and convenient.?

The hackRF sdr radio uses a somewhat similar construction.?
A xilinx cpld is used between the nxp lpc series mcu and the maxim analog baseband chip.

As for stm32f4's adc, its only 7msps in interleaved mode.
Without interleaving it's only 2.4msps.?
But that would be enough with an IF slightly below 1.2MHz

Another option to improve the RBW might be to use the SI4468 as the receiver.? These are ?2.52 plus VAT from Mouser UK in single units

According to the datasheet the digital filters can be set to minimum 0.21kHz bandwidth, and 0.26, 0.28, 0.32, 0.39, 0.48, 0.54, 0.81, 0.89, 0.96, 1.19kHz etc also seem to be available.? Frequency resolution also seems to be better than the SI4432.

Working out how to program the thing looks to be a nightmare however, definitely more complicated than the SI4432.? The narrow bandwidths would almost certainly need a TCXO to be worthwhile, and of course the pin outs are different.
Reading RSSI on wide bandwidths could also be slower extending the sweep times.? How it actually works in practice and how good the filters and RSSI readings really are will need testing.

I have ordered one to play with, but I am really busy so it will take some time before I get round to it.

Dave