Hello all!
I have an ATU-100 where I have had problems with broken SMD caps so now I have replaced them all with 3kV disk caps instead.
However when I measure the capacitance between center and ground in test mode I get non-linear values out when stepping through the 128 different combinations.
I understand it is probably due to my capacitors are not exact in value as the spec says some % more or less.
My idea is to make the stepping through all possible combinations as linear as practically possible by adding or removing capacitance.
My question is what to write to the EEPROM settings regarding the cap values? Is it the exakt measured values of the capacitors before inserting or is it the measured values between center and ground connector? When measuring both stray capacitans and inductance are involved in the actual values.
It could be that the software compensates for known stray capacitance on the PCB as it should be possibly known at time of designing the software and fairly consistent between PCBs when manufactured.
Also, does the software do a deacent job even if there are non-linearities in the capacitor range?
And also, is my method not good as I measure the capacitance using a frequency around a few hunder khz which could possibly affect measured values due to stray inductance?
By 'non-linear' above I mean that when increasing the binary value the capacitance actually get lowered. This happens if e.g. capacitor value activated by bit 4 is lower than the combined capacitors of bit 3, 2, 1 and 0 when switching from value 15 to 16.
