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Thanks Ryan, I missed your write up. I'm hoping it will not be too
difficult to modify one for 160M.

I wrote this transceiver up on my website if anyone cares for an analysis:



TL;DR: It's SSB transmit, DSB receive.
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Just like the Warbler and PSK series of days long ago, K1SWL has done
it again by teaming up with N2APB to produce a phasing SSB QRP
transceiver for FT8 and other digital modes. With two frequencies
available and a cost of only $50 per band, we can put our DSB toys out
to pasture.

Kits start shipping Dec. 16th:

I've ordered two thus far.

N1ESE

Easy enough.
Let's expand that range to all values from 0.0000001 F to 100000 pF.
What more could you want?? ?;-)

Jerry, KE7ER

??

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http://vakits.com/ceramic-capacitor-kit-50-values

The Si5344 apparently does not support programmable phase shifts.
Jerry

Hans,

So the VCO in the Si5351 seems to work from roughly 200 mhz to 1200 mhz.
The max is 6 times the min, absolutely amazing!
I had assumed the VCO was a straight up analog oscillator using a varactor diode,
can't imagine how it can have that much range.
It's like building a stable VFO that sweeps from 80m up to 15m in one go.

The phase shifting is in the Si5351 to allow digital clocks to be lined up,
compensating for different trace lengths and different clock setup times within IC's.
We are indeed lucky that this works so well for quadrature clocks.

Curious that the third overtone 27mhz crystal gave a 9mhz reference.
I had been thinking that the shaky results when driving 10mhz into the crystal oscillator pin
were due to an internal 25-27mhz bandpass filter, allowing overtone crystals to be used.
I was wrong.

Excellent write up on measuring phase noise, not something I know much about.
And to prove it, I will wonder aloud if a DC receiver (with a very stable LO)
could measure phase noise, just analyze the resultant audio.

The ham community has zeroed in on the Si570 (the first one that was easy to use)
and the Si5351 (really really cheap).??
There are several score of such parts that SiLabs has now,?
and a few from other manufacturers as well.?
Hard to keep track, especially since their selection guide is organized so poorly:
? ??
They try to bust the product line into groups by application, which I find absurd,
Smells like a decision made by some middle manager rather than an engineer.
Or perhaps whoever it was that wrote AN619.
I just want to know if it's i2c/spi programmable, cheap, range, jitter, etc.?
Spend 10x the price of an Si5351 and jitter can be vanishingly low, an spi interface
would make it fast enough to synthesize eer type SSB transmissions.
Would be nice to at least have one on the bench as a signal generator.
If a PCB and some C code were available for something like the Si5344,
it might take off within the ham community.

Jerry, KE7ER

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I wrote:? "I wonder if that VCO/4 step size is by design or just a happy coincidence."

I'm betting happy coincidence,
perhaps a result of the tricks they play to get low jitter fractional divides.
The Si5351 is targeting cheap crystal oscillator replacement.

As I recall, nothing in the extensive lineup of SiLabs programmable oscillators?
tries to target quadrature signal generation.

Jerry

Hans,

Good stuff!

Table 5 of the datasheet says crystal reference oscillator on the Si5351 can be 25 to 27 MHz,
but that the Si5351-C in the QFN20 with the separate CLKIN pin can take a reference anywhere between 10 and 100 MHz.
Somebody in one of the other forums (bitx20?) was playing with driving an external clock into a crystal oscillator pin?
on our cheap Si5351-A in the MSOP8, it worked (I believe down to 10 MHz) but phase noise got quite bad.
Apparently the amp behind the crystal pins really does want to be somewhere up around 25-27 MHz.

Page 3 of AN619 does say the PLL feedback MultiSynth divider can have a range of 15.0 to 90.0..
The why of 90.0 makes sense, if the RFCLK is 10 MHz then we need 90.0 to put the VCO at 900 MHz.
The 15.0 minimum strikes me as just wrong, as is much of the other stuff in that section.
If the datasheet is correct and REFCLK can be 100 MHz, than that PLL divider
would have to go down to 6.0 in order to bring the VCO down to 600 MHz.
Perhaps the original plan at SiLabs was targeting a REFCLK max of 40MHz:? 40*15=600
but they later found it worked fine up to 100MHz?
I'd guess it is the same MultiSynth as the output divider, and that both the 90.0 and 15.0
are not hard limits.? Have you ever tried going below a ratio of 15.0?

When pressing the lower limits of the VCO frequency, we may be getting more phase noise
due to the PLL loop filter having been designed for 600 to 900 MHz.
But since we have the rather large 126.0 output divide ratio,
the phase noise of our output signal is still quite small.

The Nanovna guys apparently read your forum postings, as they are running the VCO up around 1200 MHz.
Using the third and fifth harmonics of the 300 MHz square waves coming out, the Nanovna
is now giving useful results up beyond 1GHz.? Amazing stuff for a VNA you can buy for $40.
? ??/g/nanovna-users

Once you go to integer mode on the output divider (not fractional mode as in the si5351bx routines),
the phase register of CLK1 pretty much has to be locked to that output divide ratio
to generate quadrature clocks.? I wonder if that VCO/4 step size is by design or just
a happy coincidence.

>? a 14MHz crystal available, then this would also work - giving a minimum output frequency in quadrature mode, of 14 * 15 / 126 = 1.67MHz.?

Wow, that puts the VCO at 14*15=210 MHz, far far below the 600 MHz spec.
Have you tried this?

By the way, feel free to steal any of my comments (from any forum) that you find useful
in your QRP-Labs reading material.
And maybe even credit KE7ER if it is not being presented as a wrong headed counter-example.

Jerry,? KE7ER

This section from Hans' FDIM writeup is key:

"The MultiSynth division ratio has a minimum of 4 (for output frequencies over 150MHz). The phase offset register has a maximum value of 127. Since we are setting the phase offset register to the same value as the divider, and the divider is an even integer, this limits the maximum divider value to 126. It places a lower limit on the output frequency for which 90-degree quadrature can be obtained. Practically speaking, with a 27MHz reference oscillator crystal, the lowest frequency at which the Si5351A configuration supports quadrature LO on two outputs, is 3.2MHz."

He is speaking of the output MultiSynth dividers which divide down what comes out of the VCO to
a frequency that is then presented on one of the output pins CLK0, CLK1, or CLK2.
It is easy to create such a digital divider for integer ratios, the Si5351 uses the name "MultiSynth"
to remind us that these dividers can have a 20 bit fractional part, giving a resolution of a few parts per billion.
In addition to the output multisynth dividers, the front end PLL also has a fractional MultiSynth divider to allow the VCO
frequency to be set to arbitrary frequencies at very high resolution, locked to the 27 mhz crystal reference.?

This business of setting the phase offset register to be equal to the output divider MultiSynth value might be a bit puzzling.
Assume for a moment that you can set the output dividers for CLK0 and CLK1 both equal to 1 (you can't, minimum is 4).
And that the VCO is operating at 600 mhz.
So there will be a 600 mhz signal present on both the CLK0 and CLK1 pins.
We want a phase shift on CLK1 of 90 degrees with respect to CLK0, or 1/4 of 600 mhz.
Assume the phase shift register of CLK0 is set to 0.
Since the phase shift registers are calibrated in units of VCO/4, we set the phase shift register for CLK1 to 1,
which is equal to the output divider register of 1.

Hans restricts the output dividers to be a multiple of 2, since SiLabs states that this gives the least phase noise on the output clocks.
Let's say we now divide the VCO by 100, giving 6.0 mhz on both CLK0 and CLK1.
The required delay on CLK1 with respect to CLK0 will now be 100 times greater than it was when we had 600 mhz going out,
so the CLK1 phase shift register is now 100, equal to the output multisynth divide ratio.? CLK1 is still 90 degrees after CLK0.

Hans states that the maximum value for this output divide ratio is 126 since it must be even,
and must be equal to the phase shift register which has a maximum value of 127 (the register has 7 bits).
So with the largest possible divide and the lowest (by spec) VCO of 600 mhz, we get an output of 600/126 = 4.762 MHz
If we want to hit 3.5mhz, we need to cheat on the VCO and bring it down to 3.5*126 = 441 MHz.
Hans has found that this consistently works.

Locking the phase shift register to be equal to the output multisynth register is a major win,?
one I didn't see coming.? By doing so we put the phase shift at exactly 90 degrees.
If we were to just set the output clock to some arbitrary value (perhaps using fractional output divider values),
and then calculate the contents of the phase shift register, the granularity of the phase shift we get
will mean significantly greater errors in the relative phases of the two clocks.

And don't forget that other key section from his paper:
"do a PLL reset only once at the beginning, and thereafter every time the MultiSynth Divider and phase offset parameters are set."
Once that gets set up you can move the VCO around at will without doing any resets, within the allowable range of the VCO.
By the datasheet, this is 600 to 900 MHz.
By Hans, you can cheat and go between something like 400 and 1200 MHz.

A minor bit of confusion:
> Practically speaking, with a 27MHz reference oscillator crystal, the lowest frequency at which the Si5351A configuration supports quadrature LO on two outputs, is 3.2MHz."

I doubt the reference oscillator frequency has anything to do with this.
The VCO can be set to anywhere in its range (600-900 mhz, according to the datasheet)
within a few parts per billion using the PLL fractional divider.
What limits the minimum frequency available from an Si5351 is the minimum VCO frequency,
at 3.2mhz the VCO will be down at? 3.2*126 = 403.2 mhz.? Well below the 600mhz datasheet minimum.

TL:DR
If that's confusing and you need quadrature clocks for anything between 3.5 and 200 mhz,
give Hans $33 for his Si5351 VFO that takes care of it all for you.
A very good deal, includes display and encoder and lots of cool features in firmware.
? ????

Jerry, KE7ER

Thanks Jerry, that's what it was. The FDIM paper you linked to ended up on QRP Quarterly - just like his 2019 presentation about the design challenges of the QSX also got published in the current issue of QRP Quarterly.?

Karl Heinz - K5KHK

Hans is selling a complete Si5351 VFO with uC and display that gives quadrature clocks for $33:
? ??
Given all the features, that's a very good deal.
Not sure, but I don't think Hans has released the code.
Perhaps the etherkit library implements phase shifting, but even then it may take a few days to get working properly.

The register of interest is the "Initial Phase Offset" for each channel, registers 165 to 170:
? ??
It is 7 bits unsigned, the LSB is one quarter of the internal VCO period, minimum VCO frequency is 600mhz.
So maximum shift is 2**7 * 1/(600e6 * 4) = 53.33 nanoseconds.
Shifting one of the clocks by 90 degrees, our output quadrature clocks can be as low as 1/(4*53.33ns) = 4.687 MHz.
As you go up in frequency you can raise the VCO up to 900 mhz, beyond that the accuracy of the 90 deg phase shift
degrades since the phase shift resolution is always 1/4 of the VCO period.

Hans has found that the VCO in the si5351 works well enough below 600mhz (and up to almost 1200mhz).
To get a 90 degree phase shift at 3.5mhz, the VCO would have to be down around 448mhz

I don't get QRP-Quarterly, would like a pointer to the article if it exists.
Here's an FDIM paper that Hans presented, including a full description of quadrature clocks from the Si5351:
? ??
In it, Hans mentions how he uses integer divides on the output multisynths, fine tuning is done by manipulating
the PLL multisynth divider.? However, as the uBitx has shown, using fractional output multisynths with a fixed VCO
works just fine, this is necessary on the uBitx to generate the three independent clocks.
Small frequency transitions are glitch free when using fractional output multisynths,
and though phase noise is?worse than would be with integer output multisynths
(I believe within a factor of 2), the phase noise still far better than the typical analog VFO.

There are differences? between my analysis above and his FDIM write up.
He doesn't mention the issue of bringing the VCO below 600mhz.
You would do well to study his writeup closely, as what he has done clearly works.

If I were doing a one-off from scratch, I'd probably just put down an si5351 and a 74AC74.?
At least as a first pass.

Jerry, KE7ER