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Hans,
Good stuff! Table 5 of the datasheet says crystal reference oscillator on the Si5351 can be 25 to 27 MHz, but that the Si5351-C in the QFN20 with the separate CLKIN pin can take a reference anywhere between 10 and 100 MHz. Somebody in one of the other forums (bitx20?) was playing with driving an external clock into a crystal oscillator pin? on our cheap Si5351-A in the MSOP8, it worked (I believe down to 10 MHz) but phase noise got quite bad. Apparently the amp behind the crystal pins really does want to be somewhere up around 25-27 MHz. Page 3 of AN619 does say the PLL feedback MultiSynth divider can have a range of 15.0 to 90.0.. The why of 90.0 makes sense, if the RFCLK is 10 MHz then we need 90.0 to put the VCO at 900 MHz. The 15.0 minimum strikes me as just wrong, as is much of the other stuff in that section. If the datasheet is correct and REFCLK can be 100 MHz, than that PLL divider would have to go down to 6.0 in order to bring the VCO down to 600 MHz. Perhaps the original plan at SiLabs was targeting a REFCLK max of 40MHz:? 40*15=600 but they later found it worked fine up to 100MHz? I'd guess it is the same MultiSynth as the output divider, and that both the 90.0 and 15.0 are not hard limits.? Have you ever tried going below a ratio of 15.0? When pressing the lower limits of the VCO frequency, we may be getting more phase noise due to the PLL loop filter having been designed for 600 to 900 MHz. But since we have the rather large 126.0 output divide ratio, the phase noise of our output signal is still quite small. The Nanovna guys apparently read your forum postings, as they are running the VCO up around 1200 MHz. Using the third and fifth harmonics of the 300 MHz square waves coming out, the Nanovna is now giving useful results up beyond 1GHz.? Amazing stuff for a VNA you can buy for $40. ? ??/g/nanovna-users Once you go to integer mode on the output divider (not fractional mode as in the si5351bx routines), the phase register of CLK1 pretty much has to be locked to that output divide ratio to generate quadrature clocks.? I wonder if that VCO/4 step size is by design or just a happy coincidence. >? a 14MHz crystal available, then this would also work - giving a minimum output frequency in quadrature mode, of 14 * 15 / 126 = 1.67MHz.? Wow, that puts the VCO at 14*15=210 MHz, far far below the 600 MHz spec. Have you tried this? By the way, feel free to steal any of my comments (from any forum) that you find useful in your QRP-Labs reading material. And maybe even credit KE7ER if it is not being presented as a wrong headed counter-example. Jerry,? KE7ER |
