Mike, sorry for the late reply, I'm rather busy at work at the moment.
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Thank you for confirming that it is the combined divider ratio from VCO frequency to output frequency that determines the required phase offset.
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The fact that the division ratio reduced the phase offset is not intuitively clear to me, but I obviously have the wrong mental model of how the synthesizer architecture works.
I'm curious if anyone knows how the internal architecture achieves the delay?
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If the delay were to come right after the VCO output before the input into the multisynth and R divider combination of CLK1, the 90 degree phase relationship between CLK0 and CLK1 should be kept regardless of divider ratio as long as it is identical for CLK0 and CLK1.
Why would CLK_PHOFF be specified in terms of 1/4 of the VCO period if the delay doesn't directly follow the VCO?
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Thank you!
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73, Elia DL1YE
