David,
I'm trying to understand all this, and you are obvious an expert so I have a dummy question.
I added a simulation tool to my VNA software that uses a electrical model to calculate the input for the ADC of the nano VNA (the audio samples) and than the SW has to re-produce the values specified in the model. Its a great way to test and debug your SW.
When I use an "Open" and I apply a 1 cm increase of the length to the reference plane with a sweep from 1-900MHz and I compare it with a 1.3pF capacity over the "Open" I can not see the difference in the output of the VNA between addince 1cm and adding 1.3pF. Except a minute difference in the shape of the jX over frequency.
For Load the shift in reference plane does not change R and jX and for Close the capacitance does not make a difference but the shift in reference plane does.
So when you talk about "as it¡¯s just adding unwanted capacitance.", isn't that unwanted capacity not the "same" as "adding one cm in distance to reference plane" when you are measuring Open and Load?
So for calibration, should the reference plane AND the stray capacitance (and inductance) be constant and ONLY the resistance change????
