On 3/23/21 7:48 PM, Roger Need via groups.io wrote:
On Tue, Mar 23, 2021 at 07:24 PM, jmr wrote:
I've not actually looked inside my nanovna but a quick glance at the online
schematic shows a classic resistive bridge. When you connect a test circuit to
the CH0 input the bridge in the nanoVNA should output a signal that measures
to have the magnitude of the reflection coefficient. It will also have the
phase of the reflection coefficient. The LO + NE612 mixer converts this down
to 5kHz where it can be sampled with an ADC and measured in relation to the
reference signal in terms of amplitude and phase. The reference is also mixed
down to 5kHz.
If the ADC after the NE612 mixer says the 5kHz signal is shrunk to 99.9% of
the size of the 5kHz reference input then the reflection coefficient is 0.999.
If the 5kHz signal has a phase of -112degrees with respect to the 5kHz
reference then the angle of the reflection coefficient will be -112degrees.
That's the way I assume the system works. I don't see why you and Jim think
the bridge generates I and Q signals. What am I missing here?
JMR,
Please read carefully what I wrote. I did not say the "bridge generates I and Q signals". But it is not as simple as you say. Here is edy555 commenting on the original design. How is it done now? I don't know...
/g/nanovna-users/files/Miscellaneous/NanoVNA%20design%20notes%20by%20edy555/Calculate%20reflection%20coefficient%20from%20NanoVNA%20signal%20and%20plot%20frequency%20characteristics.pdf
Rather than you or I speculating I hope someone here that knows the firmware details can comment.
The I/Q measurement is done in dsp.c, in routine dsp_process() which takes 48 raw samples in *capture and turns it into two I/Q pairs.
*capture is 32 bits, the low order 16 bits are the reference, the high order bits are the measurement.
The actual calculation takes the two 16 bit numbers (input and either sin or cos) multiplies them, then divides by 16? and adds it to an accumulator. I assume the divide by 16 is to make sure that the sum doesn't overflow when summing 48 copies.? The sin and cos table is pretty close to full scale (32698, full scale would be 32767), so I assume the gain in front of the adc (or the signal levels) so that the divide by 16 and sum over 48 keeps it from overflowing.
