I see thereis a higher AUDIO codec ref clock set now
// Define aic3204 source clock frequency (on 8MHz used fractional multiplier, and possible little phase error)
//#define AUDIO_CLOCK_REF ( 8000000U)
// Define aic3204 source clock frequency (on 10752000U used integer multiplier)
#define AUDIO_CLOCK_REF (10752000U)
// Disable AIC PLL clock, use input as CODEC_CLKIN (not stable on some devices, on long work)
//#define AUDIO_CLOCK_REF (86016000U)
With 8MHz it worked stable here. Should I try with 8MHz?
