开云体育

Hi,

I have a design I'm working on that has a couple high voltage traces.? I wanted to denote this graphically with a net class directive.? What I've found, though, is that the resolved netclass for this trace is Default, regardless of whether I place the directive on the super- or sub-page.? The only way I've gotten it to resolve correctly is when I place the directive on every sheet where the signal appears, which I'm not a fan of.? Is this the only way to make it work?

The ERC should also probably catch this error, which it currently?isn't.? While I don't know what's happening under the hood, it seems like it should be treated similarly to a conflicting netclass assignment.

ERC catches this error:

ERC fails to catch this error.? Note that both cases resolved to Default:

Removing the hierarchical?connector makes it resolve as expected.

For these three examples, the sheet pin was present one sheet up, but the signal was left unconnected without a netclass assigned at this level.

?- Jason

--

	Jason Bens Product Design & Engineering
	?
?|? ?|? t:?+49 160 273 86 34 HRB 239206 B, Amtsgericht Charlottenburg(Berlin), Gesch?ftsführer: Gerard Sanders und Tim Dieryckx.