Charlls Quarra wrote:
Hi,
I have my own schematics in structural vhdl and i'm
compiling it using alliance vhdl compiler, which
produces a hierarchical netlist with the components i
want to place and route in the alliance logical format
.al, which can be translated into EDIF(.edi),
SPICE(.spi/.sp/.cir), .vlg or .vst netlists. Are any
of these netlist formats amenable for kicad to import ?
Im just curius, are you talking about generating the netlists for the transistors after map them to the library to
get an schematic with transistors in kicad? If so... nice approach, but how can this be useful? You are not going to
use discrete transistors for your VLSI design....
Saludos, Juan Pablo.
--
Juan Pablo Daniel Borgna -- Tcnico Electrnico
INTI-Electrnica e Informtica
Direccin: Avenida General Paz 5445 entre Albarellos y Constituyentes
CC157 (CP B1650KNA) San Martn, Bs. As., Argentina TE:+(5411)4724-6200
