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I am trying to create a vector of modules and am stuck at the Literal#... provisos issue. A sample code is as follows typedef struct { Bit#(1) en; Bit#(1) ok; } st_foo deriving(Bits,Eq); ..... Vector#(10,Reg#(st_foo)) csrreg ; csrreg ← replicateM( mkCSRReg( 0,0 ) ) ; .... This code gives an error of The provisos for this expression could not be resolved because there are no instances of the form: Literal#(zbc::st_foo) Any help in root causing and fixing the error is welcome. -- https://www.facebook.com/vijayvithal.jahagirdar https://twitter.com/jahagirdar_vs http://democracies-janitor.blogspot.in/

Hello! I'm trying to write a simple parser for DIMACS CNF (https://jix.github.io/varisat/manual/0.2.0/formats/dimacs.html) files in BSV. Now I'm at an early beginning in solving this task, and I try to write a function, that reads the DIMACS file line by line. I've found only $fgetc and $ungetc functions for reading from file. Could you, please, explain me, what does $fgetc exactly return? Thanks, Sergey

Hello! I have a problem with define and typedef statements at Bluespec. Here is the module: <code> package mkFibOne; `define ASIZE 2 `define BSIZE 3 `define CSIZE (`ASIZE) * (`BSIZE) typedef UInt#(`CSIZE) CsizeValType; (* synthesize *) module mkFibOne(); // register containing the current Fibonacci value Reg#(int) this_fib(); // interface instantiation mkReg#(0) this_fib_inst(this_fib); // module instantiation // register containing the next Fibonacci value Reg#(int) next_fib(); mkReg#(1) next_fib_inst(next_fib); rule fib; // predicate condition always true, so omitted this_fib <= next_fib; next_fib <= this_fib + next_fib; // note that this uses stale this_fib $display("%0d", this_fib); if ( this_fib > 10000 ) $finish(0) ; endrule: fib endmodule: mkFibOne endpackage </code> I've taken the module that calculates Fibonacci sequence and I've added several defines and one typedef at the beginning. When I try to compile this, I have the following error: bsc -u -sim -simdir build_bsim -bdir build -info-dir build -keep-fires -aggressive-conditions -show-schedule -no-warn-action-shadowing -no-inline-rwire -show-range-conflict -p + mkFibOne.bsv checking package dependencies Error: "mkFibOne.bsv", line 7, column 15: (P0146) Error at `CSIZE: Incorrect number of parameters: Expected 1, found 0. make: *** [Makefile:44: compile] Error 1 It looks like CSIZE is not substituted properly at typedef. Could you help me in fixing the error? Thanks, Sergey

Is it possible to attach custom attributes to methods etc e.g. Xilinx ILA requires (*mark_debug*) Interrupts need (* X_INTERFACE_INFO = ...) etc.

I have some code on the lines of Stmt fill_buffer=seq // Bunch of Actions endseq; Stmt processBuffer_stmt=seq .... endseq; stmt fsm_stmt=seq while(packet.available) seq someaction; if( ! buffer.notEmpty())seq fill_buffer; endseq process buffer endseq endseq; I see a rule created for the line corresponding to `if( ! buffer.notEmpty())seq` and this rules can_fire depends on buffer$RDY_deq && buffer$RDY_first &&... Since that happens to the an impossible condition the FSM is stuck at that point. When I inline the code for fill_buffer, the FIRE conditions are correctly generated. Does bluespec support nested StmtFSM statements? If not is there a better way to group repeated action sequences?

Is it possible to organize an access to common data from different BSV modules ? For example, at top level module I have several memory blocks (BRAMs, I guess) and I want to read/write from/to them from sub-modules. Are there any examples of such structure? Thanks, Sergey

How to access a variable in submodule to topmodule? Reg#(File) fh <- mkReg(InvalidFile); // declared in submodule I need to access the fh in the Top-level module. So that I can write the simulation fdisplay results in Top-module as well as the fdisplay result in submodule in the same text file. Thanks in advance.

Hi, I have ring oscillator module written in Verilog which I expose to Bluespec using the ClockGenIfc and Clock interfaces. I would like to use several instances of this and use them as a source of pseudo random data by sampling them. I can use a register and toggle a bit, using each oscillator as a clock, but is it possible to expose the value of the Clock directly as a bit value and sample it as if it were an external signal from a peripheral? This will let me preserve the metastable/jitter behavior of these signals until I really want to synchronize them against a clock domain of choice. Thanks, Arjen

I have an interface, including sub interfaces, which matches pin assignments in a constraints file for my FPGA board. I have a top module implementing this interface, which defines some clocking and reset elements (PLL synthesized clocks, initial reset), which are then passed into the downstream modules implementing my design. One of these modules implements one of the sub interfaces in the top interface (which are really IO pins of the device) and I would like to directly connect these sub interfaces together, but I am running into the following error: "Method is unusable because it is connected to a clock not available at the module boundary." I understand why in the general case you do not want to allow this kind of behavior, but how does one handle the case where one or more clocks are generated internal to a module which ultimately drive IO pins of a device? I can't synchronize these this sub interface to the original input clock of the top module as that would break the IO interface. A simplified illustration of what I am trying to do: https://gist.github.com/arjenroodselaar/d1300b6c0d888b53cefb837f51c95bf3. I studied the various attributes which can be used to describe clocks/resets, I've tried declaring the IO pins as a port with a "no_clock" attribute, but I can not work out how to connect this to the submodule or to a method in the Top interface. How do I make this work?

My code contains the following lines. 809 Stmt processReq_stmt=seq ....... 820 foo_ff.deq(); 821 if(bar_ff.notEmpty()≡ True)seq // ==True is not required but added it during debugging this case. 822 baz_stmt; 823 endseq 824 endseq; My expectation is, after WILL_FIRE...l820c... is asserted. if bar_ff_EMPTY_N is '0' fsm will go to done state (mkFSMState =0) What I see is, after WILL_FIRE...l820c... is asserted. The if condition is completely ignored and the FSM goes to Can_fire of action in line 822. i.e. mkFSMState transitions from 'd32 to 'd58) Generated Verilog is 3419 WILL_FIRE_RL_processReq_fsm_action_l820c37: 3420 processReq_fsm_state_mkFSMstate_D_IN = 6'd58; foo_ff and bar_ff are both of type FIFOF Am I missing something?

Hello! I've written the include file with a number of defines: `define MAX_VAR_NUM 1024 `define MAX_CLS_NUM 8192 `define MAX_VAR_CLS 32 `define MAX_LIT_NUM TMul#(`MAX_VAR_CLS, `MAX_CLS_NUM) `define MAX_VAR_MEM_SIZE TMul#(`MAX_VAR_NUM, 2) `define VAR_IDX_WIDTH TLog#(`MAX_VAR_NUM) `define CLS_SIZE_WIDTH TLog#(TAdd#(`MAX_VAR_CLS, 1)) I've used these defines at BSV module with "`include" directive, but the compiler returns the following error on the last line: Unexpected `#'; expected `{', operator, SV 3.1a keyword `matches', `&&&', `?', `,', BSV 3.8 keyword `provisos', or `;' What did I miss?

Is it correct for BSV to use functions to create a number of BRAMs? I've wrote the following code: typedef 1024 MaxVarNum; typedef 8192 MaxClsNum; typedef 32 MaxVarInCls; typedef TLog#(MaxVarNum) VarIdxWidth; typedef TLog#(TAdd#(MaxVarInCls, 1)) ClsSizeWidth; typedef TAdd#(VarIdxWidth, 1) LiteralWidth; typedef TAdd#(ClsSizeWidth, TMul#(MaxVarInCls, LiteralWidth)) ClsSize; typedef UInt#(ClsSize) ClauseUInt; typedef Bit#(ClsAddrWidth) ClsAddrWidthBit; typedef TDiv#(MaxClsNum, 4) ClsBankSize; typedef TLog#(ClsBankSize) ClsAddrWidth; typedef struct { ClauseUInt data; } Clause deriving (Bits, Eq); typedef BRAM2Port#(ClsAddrWidthBit, Clause) ClauseBRAM; function ClauseBRAM mkClauseBRAM(Integer blockNum); BRAM_Configure cfg = defaultValue; String fileName = "cls_mem" + fromInteger(blockNum) + "_data.txt"; cfg.loadFormat = tagged Hex fileName; cfg.memorySize = valueOf(ClsBankSize); ClauseBRAM bram = mkBRAM2Server(cfg); return bram; endfunction and compiler gave me the following: Type error at the use of the following function: mkBRAM2Server The expected return type of the function: Clause::ClauseBRAM The return type according to the use: a__#(BRAM::BRAM2Port#(b__, c__)) If it is the wrong way, then how is it possible to create a number of BRAMs inside BSV module? I suspect that some kind of "generate" is needed here.

Hello, I'm trying to implement a specific memory module (M). The problem is that it should have three "communication channels": two for read requests/responses and one for write requests. I mean that there are two modules (suppose, A and B) that send read requests to the memory module M and receive read responses from it, and also there is another module C that sends write requests only to the memory module. Here is how it is implemented in Chisel: class VarWord extends Bundle { var fixed = UInt(Config.VAR_MEM_WIDTH.W) var value = UInt(Config.VAR_MEM_WIDTH.W) } class VarReadIface extends Bundle { val en = Input(Bool()) val addr = Input(UInt(Config.VAR_ADDR_WIDTH.W)) val data = Output(new VarWord) } class VarWriteIface extends Bundle { val en = Input(Bool()) val addr = Input(UInt(Config.VAR_ADDR_WIDTH.W)) val data = Input(new VarWord) } class VarMemory extends Module { var io = IO(new Bundle { // 2 read ports (for the reader and the assigner). var read_in = Vec(2, new VarReadIface) // 1 write port. val write_in = new VarWriteIface }) val invalid_word = Reg(new VarWord) val mem = Mem(Config.VAR_MEM_LENGTH, new VarWord) loadMemoryFromFile(mem, "var_mem.txt") when(io.write_in.en) { mem(io.write_in.addr) := io.write_in.data } for (i <- 0 to 1) { io.read_in(i).data := Mux(io.read_in(i).en, mem(io.read_in(i).addr), invalid_word) } } Could you give some recommendations on how to implement this structure on BSV? I think I can use two Server interfaces for communication with A and B modules, but what interface should I take for communication with C? P.S. Dear colleagues, thank for your replies on my previous questions. I really appreciate your help!

Hello, I try to perform a "reduced or" operation (i.e. a bit-by-bit "or") on a vector of bits. Here is my code: import Vector::*; typedef Reg#(Bool) BoolReg; typedef Vector#(TotalCheckerNum, Reg#(Bit#(1))) CheckerReg; CheckerReg checkers_ready <- replicateM(mkReg(0)); BoolReg active <- mkRegU; rule somerule; Vector#(TotalCheckerNum, Bool) rdy_vals = readVReg(checkers_ready); active <= or(rdy_vals); endrule The 'TotalCheckerNum' typedef is a constant. The compiler says that there is no such "or" function: Unexpected V2K keyword `or'; expected operator or expression but the "or" function is mentioned at the BSV Reference Guide Revision: 21 July 2017 ("C.3.4 Tests on Vectors"). What can be wrong here? Thanks in advance.

I have a vector of registers and I want to initialize it. The problem is that different registers from vector should have different values. I've tried to implement this by using the specific function: typedef Vector#(TotalCheckerNum, Reg#(Bool)) BoolRegs; typedef Vector#(TotalCheckerNum, Bool) BoolValues; module Foo(Empty); function BoolValues init(); BoolValues flags = ?; for (Integer i = 0; i < valueOf(TotalCheckerNum); i = i + 1) begin flags[i] = (i % 2 == 0); end return flags; endfunction BoolRegs regs <- init; and this is wrong because the function should return a vector of registers instaed of vector of Bool. It seems that it is impossible to create registers from inside the function also. How can such vector be initialized?

Hello, Does in BSV exist a standard function, that concatenates all elements of Vector into one? For example, I have Vector#(4, Bool) and I want to convert it into UInt#(4). Thanks in advance! Sergey

Hello, I have the following code fragment inside my module. This fragment causes an "Unbound type variable `n_width'" error. module mkSomeModule#(parameter Integer n); function UInt#(5) width(Integer n); return fromInteger((n <= 1) ? 1 : log2(n - 1) + 1); endfunction UInt#(5) n_width = width(n); Reg#(Bit#(n_width)) enq_ptr <- mkReg(0); ... The "UInt#(5)" type for n_width variable was selected because of concrete values that were used upon SomeModule instantiations. Could you help me to fix this error?

Hello, I have two modules - one of them (let Foo) implements Client interface, another one (let Bar) implements Server interface. Here is Foo interface fragment: interface Foo_IFC; ... interface Client#(ClauseMemReq, ClauseMemResp) read_out; endinterface Here if Bar interface fragment: interface Bar_IFC; interface Vector#(ClsBankNum, Server#(ClauseMemReq, ClauseMemResp)) read_in; endinterface I have a vector of Foo modules at my top level module and I want to connect Clint interfaces with Server by doing something like that at special "bind_all" rule: for (Integer i = 0; i < valueOf(ClsBankNum); i = i + 1) begin mkConnection(foos[i].read_out, bar.read_in[i]); end In such case I receive: Type error at the use of the following function: mkConnection The expected return type of the function: Action The return type according to the use: c__#(Empty) How should I do in such case?

I have a vector of a struct type. I want to find the index where a field matches a variable. the `findIndex` function is the nearest match for what I want to do, But I want the predicate to take an extra argument. Is this supported? If not what is the recommended way to achieve the desired result. e.g. Reg#(Bit#(4)) var_a <-mkRegA(0); typedef struct { Bit#(4) x; Bool y; } St_type deriving(...); Vector(10,St_Type) vec; ..... Now I want to find the index(i) of the element in vec where vec[i].x==var_a Is for loop the only solution? or is there something better?

Hello, I'm trying to compile the following BSV module: typedef struct { VarMemBit fixed; VarMemBit value; } VarWord deriving(Eq, Bits); typedef struct { Bool enable; VarAddrBit address; } VarMemReadReq deriving (Eq, Bits); typedef struct { Bool enable; VarAddrBit address; VarWord data; } VarMemWriteReq deriving(Eq, Bits); typedef RegFile#(VarAddrBit, VarWord) VarMem; interface VarMemory_IFC; // 2 read ports (for the reader and the assigner). interface Vector#(2, Server#(VarMemReadReq, VarWord)) read_in; // 1 write port. interface Get#(VarMemWriteReq) write_in; endinterface (* synthesize *) module mkVarMemory(VarMemory_IFC); Vector#(2, FIFOF#(VarMemReadReq)) readReqQs <- replicateM(mkFIFOF); Vector#(2, FIFOF#(VarWord)) readRespQs <- replicateM(mkFIFOF); FIFOF#(VarMemWriteReq) writeReqQ <- mkFIFOF; VarMem reg_file <- mkRegFileFullLoad("var_mem.txt"); for (Integer i = 0; i < 2; i = i + 1) begin let req_q = readReqQs[i]; let resp_q = readRespQs[i]; rule read_request (req_q.notEmpty()); let r_req = req_q.first; VarWord response = r_req.enable ? reg_file.sub(r_req.address) : ?; req_q.deq(); resp_q.enq(response); endrule end rule write_request (writeReqQ.notEmpty()); VarMemWriteReq write_req = writeReqQ.first(); if (write_req.enable) reg_file.upd(write_req.address, write_req.data); writeReqQ.deq(); endrule Vector#(2, Server#(VarMemReadReq, VarWord)) bank_vector = newVector; for (Integer i = 0; i < 2 ; i = i + 1) bank_vector[i] = ( interface Server#(VarMemReadReq, VarWord); interface Put request = fifoToPut(fifofToFifo(readReqQs[i])); interface Get response = fifoToGet(fifofToFifo(readRespQs[i])); endinterface ); interface read_in = bank_vector; interface Get write_in = toGet(writeReqQ); endmodule The Bluespec Compiler returns the following error log: Error: "VarMemory.bsv", line 40, column 8: (T0032) This expression requires the following proviso which could not be resolved: Bits#(VarMemory::VarMemReadReq, a__) The proviso was implied by expressions at the following positions: "VarMemory.bsv", line 42, column 61 An instance for this proviso exists, but it depends on the following proviso for which there is no instance: Add#(1, TAdd#(TLog#(0), 1), a__) Error: "VarMemory.bsv", line 40, column 8: (T0032) This expression requires the following proviso which could not be resolved: Bits#(VarMemory::VarMemWriteReq, b__) The proviso was implied by expressions at the following positions: "VarMemory.bsv", line 44, column 39 An instance for this proviso exists, but it depends on the following proviso for which there is no instance: Add#(1, TAdd#(TAdd#(TLog#(0), 1), 256), b__) It is hard for me to interpret these errors. Doy you have any ideas on how to fix them? Thanks in advance.