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For some context, here ( https://git.joyofhardware.com/ReferenceProjects/riscv-bluespec-classic/src/commit/b4c7537a8542fdb2e9d67cf52c76167e9c231ef4/bs/Bus.bs#L27 ) is where I'm using `mapM_`.

I'm currently trying to instantiate an Arbiter and call request for each client in `Arbiter_IFC.clients` in a rule. Its seems that `Vector.mapM` is the tool to get the job done?

Thank you the detailed response!? It has greatly enhanced my understanding of how BSC actually leverages provisos.? The key bit was this: I had been assuming something much more magic: that it

Thank you for the comprehensive reply! And for the pointer to the RISC-V design course, I'd been meaning to read it in more detail but forgot about it. Your reasoning makes a lot of sense to me. In

You may want to look at the Fife 5-stage RISC-V pipeline in: https://github.com/rsnikhil/Learn_Bluespec_and_RISCV_Design In 'Code/src_Fife/' you will find the 5 CPU pipeline stages S1_Fetch.bsv

(I appreciate that this is a subjective question and the general answer is "it depends", but gut wisdom and opinions from experienced Bluespec programmers would be very welcome!) I'm writing a modest

There may be other state that the rules are using, which enforce an order. But if the rules can equally execute in either order, then BSC will arbitrarily pick an order, and will report a warning

As Nikhil said, there is a conceptual sequence of rules within a clock cycle, with a rule calling 'deq' coming first followed by a rule calling 'enq' (for 'mkPipelineFIFOF'). That means that there

It's better to think first in terms of 'before' and 'after' each rule r1 containing an 'enq' or 'deq', and only then in terms of clocks, because the changed state from r1 can be visible to another

It seems that enqueueing into an empty mkPipelineFIFOF in cycle `n` won't be reflected in its `notEmpty` signal until the beginning of cycle `n+1`? Likewise, if you dequeue a value from a

Ok... This is quite fascinating and makes sense... I suppose if we evaluate a model action by action, two actions that write to the same resource one after the other can be reduced to the last write

If you give the -show-rule-rel flags, or query the schedule information from within the BDW GUI or using Blutecl commands, the tools can show you what method calls contribute to the inferred rule

I might have an idea about how the compiler does this... Under the hood, can Bluespec rewrite rules into multiple rules? That is, can a rule be split into two rules for the purpose of reasoning about

And here is the link to the relevant code: https://git.joyofhardware.com/ReferenceProjects/riscv-bluespec-classic/src/commit/271148e53840b2fd5fdc33e742e9831b50a7b857/bs/TagEngine.bs

I’ve been digging into the scheduling behavior of my TagEngine implementation and could use some insight from the community on how Bluespec resolves conflicts between methods and rules, particularly

Can you define specific instances to synthesize? For example: {-# synthesize mkTagEngine5 #-} mkTagEngine5 :: Module (TagEngine 5) mkTagEngine5 = mkTagEngine and then synthesize that, and call

Synthesis boundary may not be an option for me as bluespec complains about TagEngine being polymorphic. Also, I tried building BDW for Mac in 2022 and didn’t have much luck… Maybe it’s better

There's a GUI environment called BDW, available in the repo bdw <https://github.com/B-Lang-org/bdw>, which automates the connection to the GTKwave VCD viewer and provides the scripts for displaying

Thanks, Ed! Making a built-in typeclass would still have some benefits, it's worth noting. The SMT solver won't know anything about your user-defined typeclass, so it won't be able to use that

I already added `-keep-fires` here <https://git.joyofhardware.com/ReferenceProjects/riscv-bluespec-classic/src/branch/tag_engine_version_3/Makefile#L50>. The issue I’m having is that the generated