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I am trying to create a vector of modules and am stuck at the Literal#... provisos issue. A sample code is as follows typedef struct { Bit#(1) en; Bit#(1)

The problem here is that mkCSRReg expects you to provide it an st_foo and you are passing it the literal 0 (which under the covers is converted to an st_foo via the fromInteger function defined in

Nirav, Thanks. Looks like I have not properly understood the return type of a module instantiation, After fixing the above, I am seeing a similar error. **Note** the commented function throws a

Ah. You've stumbled onto one of the trickier parts of the typing system, but you can mostly avoid the details by using module instead of function when you return anything with a module (e.g. fnCSR).

Hello! I'm trying to write a simple parser for DIMACS CNF (https://jix.github.io/varisat/manual/0.2.0/formats/dimacs.html) files in BSV. Now I'm at an early beginning in solving this task, and I try

Hi Sergey, If you are parsing a file at run time of the simulation, you might find it easier to write that as C code and import it into BSV as one or more functions, using the import-BDPI

Hi Julie, Thanks for the exhaustive answer. Sergey

Hello! I have a problem with define and typedef statements at Bluespec. Here is the module: <code> package mkFibOne; `define ASIZE 2 `define BSIZE 3 `define CSIZE (`ASIZE) * (`BSIZE) typedef

Is it possible to attach custom attributes to methods etc e.g. Xilinx ILA requires (*mark_debug*) Interrupts need (* X_INTERFACE_INFO = ...) etc.

It's been a while since I've dealt with the nitty gritty of the preprocessor, but that looks like it should work. That said, the easiest fix is probably to replace your `defines with typedefs. It's

Dear Nirav, Thank you for quick answer:) I've subsitituted defines by typedefs, and the error is gone. Do you think it is a correct behavior for Bluespec proprocessor?

The bluespec preprocessor should match the behavior of the verilog preprocessor, but I'm pretty the preprocessor is working correctly. Thinking on it some more, I think the issue is that we don't in

Yes, if I change "*" to TMul, it works both for defines and typedefs. Again, thank you, Nirav.

I don't believe that BSC supports "pass-through" attributes. Although this is a feature that probably should exist and is probably not too hard to implement. This is because BSC does support a "doc"

Julie, Thanks for the suggestion of using doc attribute, I tested it on a few declaration and can confirm it partially works, I Should be able to use this to insert some of the debug logic. e.g. on

Wire and register modules are inlined, so there is no instantiation to put the comment on. If you want to prevent wires from being inlined, there are hidden flags -inline-rwire and -inline-reg (which

Is it possible to organize an access to common data from different BSV modules ? For example, at top level module I have several memory blocks (BRAMs, I guess) and I want to read/write from/to them

You can pass the shared module as a parameter to the submodule. module mkSubModule#(SharedMemoryBlock block)(Interface) <use block> endmodule Note that if you use this structure in the final

Hi, I have ring oscillator module written in Verilog which I expose to Bluespec using the ClockGenIfc and Clock interfaces. I would like to use several instances of this and use them as a source of

What Nirav said; you most likely want to invert the composition of your modules. One way to do this is to make the BRAM a Server and have all the modules who need access to this data implement the