Thanks for that code! I'm wondering how I can make it parametrizable... So far - no luck!
import Vector::*; // Required for Vector
module mkTop #(parameter Integer bitWidth) (Empty); // No default value
// Parameterized module with configurable bit width 'n'
module mkRegJ #(Integer i, parameter Integer n) (Reg #(Bit #(n)));
let r <- mkReg (fromInteger (i));
return r;
endmodule
// Helper function to instantiate mkRegJ with a fixed bit width
function ActionValue #(Reg #(Bit #(bitWidth))) mkRegJFixed(Integer i);
return mkRegJ(i, bitWidth);
endfunction
// Use mapM with the helper function
Vector #(6, Reg #(Bit #(bitWidth))) v_rgs <- mapM (mkRegJFixed, genVector);
rule rl_once;
for (Integer j = 0; j < 6; j = j + 1)
$display ("v_rgs [%2d] = %2d", j, v_rgs [j]);
$finish (0);
endrule
endmodule
$bsc -u -verilog mkTop.bsv
checking package dependencies
compiling mkTop.bsv
Error: "mkTop.bsv", line 17, column 28: (T0008)
? Unbound type variable `bitWidth'
?
