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Re: Using Z80MC SIO RAM BANKS

 

It means if you are using the monitor to load at 0000, you can't, rom is there.
also 0000 is the start address for the eprom so it will bark at you.
?
The rom has to be there to run and communicate with the buttons.? Its
why I suggested reading the V15 code to understand what the rom
does and the memory map it expects.
?
If you wanted to run code at 0000 for some reason then you need to
put a (new) monitor in high ram then enable the low ram bank. The
code in High ram allows you to talk to the machine rather than crash it.
?
The design is such that from 8000h and up is always ram.
?
FYI CP/M enables low ram and loads itself in high ram.? Once you get the
startup message you have 64K of ram with CP/M eating about 8k of the
high end of the ram.? It reserves 0-100H as system page and from 100 to?
end of the TPA as program space.? ?The TPS is Transient Program space
and something like 56K.? Asm, DDT, Stat, PIP, and a few other are tools
in the uSD.? That's my normal development environment.
?
?
Allison
Re: Using Z80MC SIO RAM BANKS

 

Thank you Allison for your explanation and patience.
I turn on the CPU Card+SIO+FP combination, wait for loading from SD with message FL 0030
Then F+E soft reset to stop PC from moving, I think it is executing CP/M
Click on "9" to set RAM bank to 0 "RAM 0"
Set PC to 0000
Set BC to 0000
Enter program (example from the manual) into 0000 (3C C2 00 80 03 C3 00 80)
Verify PC and BC are 0000
Then press 4 "go" to execute the program from RAM address 0000 SIO Bank 0
It crashes with HARD 01
Same steps when entered into 8000 works fine, I can see BC is counting up.
What am I doing wrong? Does this mean I cannot run a program from SIO RAM Bank?
Thank you,
Kerem
Re: Using Z80MC SIO RAM BANKS

 

Also read and understand ZMCv15 which is about the erom contect monitor and Basic.
?
How register are used is in there and also the memory mapping bits.? AS Z80 code
its loaded with good examples.? Its not trivial code!
?
That means reading Z80 code and understanding it.? ?Lee did a decent job of
organizing and commenting the code.? ITs in a Zip file in the files area.?
?
/g/Z80MC/files/AllisonKB1GMX/ZMCv15.zip
?
?
Allison
Re: Using Z80MC SIO RAM BANKS

 

Depends from CP/M, yes.
From basic in Eprom, no.
?
Keep in mind when you do ram banking your changing the active memory map
and stuff may disappear or end up in the wrong place.
?
The memory map is not at all explained.
?
Base machine (no SIO) rom is lower 32K and ram U2 is always upper 32K.?
At reset EProm U3 is the lower 32K.
?
Add SIO with standard AS6c1008 128k byte ram...
That ram exists as one of 4 banks of? in the lower 32K or as 32K eprom.
How they are selected is the Bank register U5, memory decoder U4,
and bits from the output of the 8250 register.
?
Picture included of what the memory map can be logically.
?
Allison

Z80-MC-W-SIO-MEMORY.jpg

Using Z80MC SIO RAM BANKS

 

Hello,
Is it possible to run a program from Z80 SIO RAM??
With SIO installed and RAM Bank 0 selected, I can type a short program starting #8000 (CPU RAM) then point PC to #8000 and execute with no problem.
When I type the same program in #0000 (SOI RAM Bank 0), point PC to #0000, execution crashes the system. Either I get a blank no responsive front panel or HARD 01 message.
Is this the normal behavior or indicates a hardware problem?
Thank you,
Kerem
Re: NVRAM with Z80MC

 
Edited

Lee,
?
Even with NMOS 8250 and the few TTL pieces the total power is quite small
and a battery plus 5V SMP regulator will produce very long run times before
battery goes too low.
?
Haven't measured it (as all up stack) as yet but I'd expect with parts as are
supplied under 140mA at 5V which is easy to deal with for battery unless
extended operating life is needed.
?
When compared to the Z80 S100 crate with 64K ram dual serial and
FDC and two FD55GF drives (5V at 6A, 12V 1.5A ,and -12 at .20ma) the
Z80MC is power frugal.? ?FYI that was a built in 1980 system and?
no CMOS.? The other S100 crate, very full, has a 8V 25A supply for
the 5V regulator input bus and a somewhat noisy fan to cool the
boards.? ?So something like the Z80MC is way lower power needs.
?
I have lower power Z80 CMOS systems that are built to be very
low power. its needs are clock speed dependant.? About 10ma
at 4mhz and under 3ma at 1mhz.??
?
?
Allison
Re: NVRAM with Z80MC

 

I've been travelling (to VCF-East) and so have missed the start of this thread. But in general...

?

The Z80MC CPU board can be run all by itself. It's all CMOS, and draws so little current that I can run it on just the power from my RS-232 adapter. It has diodes from the two PC handshake lines and serial output to a filter capacitor. When my modem program sets the handshake lines high, it delivers 10-15mA, which is more than enough to power the 5v regulator and board.

?

You can use a NV RAM, but they generally write-protect themselves before the Z80 and related circuitry crashes from falling power. Thus whatever your program was doing when the power fails will crash.

?

As Allison noted, you can use NMI to warn the Z80 to save its state. You'd need a little circuitry to detect when the input to the 5v regulator is getting low, and pull the NMI pin low. Write an NMI interrupt handler to save the state in your NV RAM. It could be an old 60 Hz transformer-rectifier power supply that normally delivers about 8-10vdc. When it falls below about 6vdc, it pulls the NMI pin low.

?

The Front Panel uses the most power when the LEDs are active. If the Z80 stops handling interrupts, it times out and blanks the display; so standby power is pretty low.

?

When I can find them, I provide 16C450's for the SIO card. It's CMOS, and so draws a lot less power than the 8250. (The 16C550 won't work.) If you have an SD-card, the NMI handler could save the state on the SD-card.

?

Since total power consumption is pretty low, the simplest scheme might be to simply power everything from a modest size battery.

?

Lee

?

--

Excellence does not require perfection. -- Henry James

But it *does* require attention to detail! -- Lee Hart

--

Lee A. Hart

Re: NVRAM with Z80MC

 

Since most of the boards and parts are CMOS running the whole thing off a
battery and switch mode regulator (for power conversion efficiency) would
be easiest.
?
For mine that means replacing the 8250 with 16C450 and the ttl parts with CMOS.
Everything else save for leds and display are CMOS.?
?
The FP (display) and SIO (8250 and TTL) boards are the highest power consumers.
?
I've built a few all comos systems (both z80 and 80C85 based) and I can get the
power under 30ma @ 5V without effort with the system running CP/M and
application.? I use those for monitoring things (data logger) where run time on
battery needs to be greater than a full week (24x7).
?
?
Allison
Re: NVRAM with Z80MC

 

Thanks Allison and Rich for your?responses and guidance.

I have more learning to do until I can figure out how to replace the RAM with NVRAM on the CPU board, if ever practical.

In the meantime, I explored available NVRAM options for direct pinout replacement of the SIO card RAM but nothing seems to work which potentially could resolve the power up and down issues by having the NVRAM in banks of the SIO card instead of CPU card RAM.
Regards,
Kerem



On Fri, Apr 11, 2025 at 12:25?PM ajparent1/kb1gmx via <kb1gmx=[email protected]> wrote:
Kerem,
?
Makes no difference if the CPU is Cmos or Nmos as the bigger
difference is overall power consumed, usually it is only part of
the systems power needs.
?
The z80MC only senses power good where it de-asserts /Reset on
power on after delay.? It has no power fail or DC good sensing.
?
NMI is available but what action it causes is define in eprom
and likely not directly usable.? ?Asserting NMI causes a handler
to do effectively nothing as Bigboot has no specific use for it.
?
Start with the Z80 user manual (mostec or zilog) to understand
how the chip works.? All of this is close to the iron work so
understanding the CPU and how its used in the hardware
environment becomes the task.? The Z80MC and Basic manuals?
cannot even attempt to cover this or could if it were larger
than 200 pages.
?
The reason nothing was found for saving the CPU state or
restoring it as its assembly programming 101.? That and
likely the question asked would mislead most search engines
(AI or not).? It is not something that is unusual or rarely done.
Most Debugger software has it wired in.? Its also sometimes
called a Context Save or interrupt programming.
?
Generally the Z80 MC is many levels above those early days
of Altair where limited ram, no rom, dumb front panel,
no IO,?no software was the then context for users.? To do
anything you hand coded assembler and hand entered
a byte at a time.? Doing computers ca1975.
?
?
?
Allison
Re: NVRAM with Z80MC

 

Kerem,
?
Makes no difference if the CPU is Cmos or Nmos as the bigger
difference is overall power consumed, usually it is only part of
the systems power needs.
?
The z80MC only senses power good where it de-asserts /Reset on
power on after delay.? It has no power fail or DC good sensing.
?
NMI is available but what action it causes is define in eprom
and likely not directly usable.? ?Asserting NMI causes a handler
to do effectively nothing as Bigboot has no specific use for it.
?
Start with the Z80 user manual (mostec or zilog) to understand
how the chip works.? All of this is close to the iron work so
understanding the CPU and how its used in the hardware
environment becomes the task.? The Z80MC and Basic manuals?
cannot even attempt to cover this or could if it were larger
than 200 pages.
?
The reason nothing was found for saving the CPU state or
restoring it as its assembly programming 101.? That and
likely the question asked would mislead most search engines
(AI or not).? It is not something that is unusual or rarely done.
Most Debugger software has it wired in.? Its also sometimes
called a Context Save or interrupt programming.
?
Generally the Z80 MC is many levels above those early days
of Altair where limited ram, no rom, dumb front panel,
no IO,?no software was the then context for users.? To do
anything you hand coded assembler and hand entered
a byte at a time.? Doing computers ca1975.
?
?
?
Allison
Re: NVRAM with Z80MC

 

Rich,
?
That can work IF the fail rate is slow enough from initial 5V to trigger
level to assure enough work (save state).? Very iffy and depends on
precision in the supervisory device.? Also those NV-rams have their
own power fail so writing to them could be locked out.? ?The
general assumption with most supervisory chips is assuring
power good before releasing reset.? ?Less so for power fail (unsafe).
?
The big boys (DEC, DG, IBM, and others) did it by first detecting
when?main power fails (AC power) or has decayed below acceptable
limits.? That is used to provide POWER-FAIL or some similar named?
control voltage.? The also provide a set of signal to say DC-GOOD.
That is then used to trigger high priority interrupt, or in the case
of Z80 NMI (non maskable interrupt).
?
This is all assembly language work.
?
I've built systems that do the latter as most (many) supervisory
circuits have boundary cases that may fail.? Harder than it looks.
as then the power supply must have enough "hold" time before
it completely fails to regulate.? The system I still have uses the
raw DC side that is typically 6-8 volts higher than DC out (5V bus).
That gives early warning of potential power fail and? assert
NMI.? ?That was an analog supply with some larger caps to
store enough for 80-100 milliseconds of known good
regulated output.? Typically a NMI routine that preserves
state is under a few milliseconds then it self halts before
power fail.
?
Start up is a Debug monitor system with option of
restore-resume in an orderly way or do a cold start.
?
An alternate way is to have the CPU turn itself off.
Simple push button to NMI makes the system? go to
a quiescent state (stop the machine or finish disk write)
then store its state and under program control
VIA IO port (relay or electronics switch) turn off
the power.
?
The latter is used for many cases as power fail is a?
random event that may have impacts (in robotics?
you need all stop, in an orderly way!) where power
off can be a user command (or event) with
orderly shut down.
?
Startup can be restore and run or cold start depending
on system and potentially establishing? external states
for external hardware or mechanics before resuming
operation but that is a system level consideration like
a machine tool or robotics application.
?
Its a system level application or use situation programming
with hardware to support it.
?
?
Allison
?
Re: NVRAM with Z80MC

 

To add to this a bit, assume that the loss of power is unpredictable. The Z80 needs to know when a power loss occurs in order to be able to “save state” (i.e. the registers, etc.). The z80 has a non-maskable interrupt that could be triggered by the power loss through another circuit. The NMI vector would point to the save state code. But then, how long do you have to save the state??

You’d need to figure out how long it takes for the power to drop to a point where the chips stop operating (let’s say that’s 4.8v), but that timing depends on power consumption and supply voltage.? Then you can calculate how many instructions can execute in that time period, and hopefully that’s enough to save the CPU and hardware state. At 4mhz, the instructions take anywhere between 1us and about 6us. So, its “just math” so to speak.?

On power-up, you’d check a flag to see if the state was successfully saved and either re-load it or start fresh.?

NVRAM supervisory chips can sense the power fail and trigger the interrupt. I have?not tried this, but that’s the theory on how it could work but as Allison said, it’s both a software and hardware solution.?

Rich



On Thu, Apr 10, 2025 at 17:09 ajparent1/kb1gmx via <kb1gmx=[email protected]> wrote:
Its done in programming.? I do not mean in BASIC.
?
Preserving the CPU state means writing all of the registers, internal? flags,
and interrupt status, to protected ram.? Fairly easy but the on startup
(aka reset) the first code in rom has to restore all that and then continue
where the CPU was stopped on power down.? That also means the state
of hardware like serial IO.? So power down is not something to be
allowed to happen randomly and power must be maintained for some
amount of time to permit the needed programming to complete.
?
However all this interacts with the design of hardware so if power down?
happens at a random point then saving all that before the power is
collapsed completely is problematic.
?
This takes a fair amount of understanding how Z80 works and how
the circuitry around? it has to work to support it.? Generally the z80MC is
not going to make all that easy for you.
?
So the best you can hope for is that ram only holds the program and?
basic will allow you to access it on startup (many can do that).? In that
case your treating memory during power down as a rom.
?
Also you unclear on what you wish to accomplish and the question
is not clear.? ? It also suggests working with hardware ie: ram, Eprom,
and IO chips is new and unfamiliar.? My early (1970s) experience was
opposite of that I had to build hardware, understand how that
works and then write code in assembler as little to none was
available (no Basic!).? ?That lead to the need to understand the
interaction of code and hardware.? ?Programming? on the bare metal.
People? brought up with PCs rarely, if ever, do that.
?
I hope this helps to answer your question. Or ask more questions.
?
Allison
Re: NVRAM with Z80MC

 
Edited

Its done in programming.? I do not mean in BASIC.
?
Preserving the CPU state means writing all of the registers, internal? flags,
and interrupt status, to protected ram.? Fairly easy but the on startup
(aka reset) the first code in rom has to restore all that and then continue
where the CPU was stopped on power down.? That also means the state
of hardware like serial IO.? So power down is not something to be
allowed to happen randomly and power must be maintained for some
amount of time to permit the needed programming to complete.
?
However all this interacts with the design of hardware so if power down?
happens at a random point then saving all that before the power is
collapsed completely is problematic.
?
This takes a fair amount of understanding how Z80 works and how
the circuitry around? it has to work to support it.? Generally the z80MC is
not going to make all that easy for you.? It would add features not
planned for or typically expected.? that and the built in code in rom
would have to change.
?
So the best you can hope for is that ram only holds the program and?
basic will allow you to access it on startup (many can do that).? In that
case your treating memory during power down as a rom.
?
Also you unclear on what you wish to accomplish and the question
is not clear.? ? It also suggests working with hardware ie: ram, Eprom,
and IO chips is new and unfamiliar.? My early (1970s) experience was
opposite of that I had to build hardware, understand how that
works and then write code in assembler as little to none was
available (no Basic!).? ?That lead to the need to understand the
interaction of code and hardware.? ?Programming? on the bare metal.
People? brought up with PCs rarely, if ever, do that.
?
I hope this helps to answer your question. Or ask more questions.
?
Allison
Re: NVRAM with Z80MC

 

Hi Allison,
I have been researching how to preserve the CPU state before power down and restore on Z80 while using NVRAM without any luck.

How would that be done on the Z80 membership card? If I understand correctly, if it is a CMOS Z80 vs NMOS Z80, it is done automatically. I am not sure if the Z80 on my MC is CMOS or NMOS.

Perhaps that section of the Z80MC user manual can be expanded to include set up and use cases with NVRAM. If I can figure this out, I don’t mind providing the first draft notes.

Thank you,
Kerem

On Thu, Apr 10, 2025 at 11:02?AM ajparent1/kb1gmx via <kb1gmx=[email protected]> wrote:
Oh, when using NV-ram in Z80 systems one needs to preserve the
CPU state before power down.? And restore that state on power up.
?
Easier way is an all CMOS Z80 system, then battery to run CPU and
all is manageable.
?
?
Allison
?
Re: Testing the piezo speaker

 

Piezo speaker is somewhat inaccurate as its actually a resonator.
Being much louder at its resonant frequency.
?
They are best when well supported by their edges with airspace
under and over.
?
?
?
Allison
?
Re: NVRAM with Z80MC

 

Oh, when using NV-ram in Z80 systems one needs to preserve the
CPU state before power down.? And restore that state on power up.
?
Easier way is an all CMOS Z80 system, then battery to run CPU and
all is manageable.
?
?
Allison
?
Re: NVRAM with Z80MC

 
Edited

On Wed, Apr 9, 2025 at 04:07 PM, Kerem Kapkin wrote:
ST M48Z35
That's a 32K byte part. similar to 62256 as used on CPU card.
The SIO board comes with 64K byte part.
?
They can be used if pinout matches as "battery backed" Ram
which is what they are.
?
I have used them for other systems, be wary as the battery in
it does fail with time.? Experience is? 4-8 years.
?
-Can it be used besides Micro-Basic?
?
Yes, it runs CP/M and there are at least 15 different basics including
at least two Basic compilers ( I use M$-Bascom and matching
interpreter).? ? Also using CP/M it can easily run other available
languages, and a raft of other software.
?
?
Allison
NVRAM with Z80MC

 

Hello,
Anyone using NVRAM instead of RAM in Z80MC as described Z80MC Operating Manual page 4?
-Does this NVRAM replaces the RAM on Z80MC or SIO card?
-Can it be used besides Micro-Basic?
-Default recommendation is ST M48Z35. Are there other alternatives?
Thank you- Kerem
Re: Strange behavior of #8 button

 

After a few days, it seems like adding the 22k resistor between pins 1-2 of R4A did the trick. Haven't had any more issues with the #8 button.
Some things to note:
R4 is a 15k sip. That's what was in the kit. So with the 22k in parallel, that makes 8.9k ohms.
The transistors Q2, Q3 are FNJ3305 and Q5 is FNJ4303. This matches the schematic.

kb1.jpg
kb2.jpg
resistors.jpg

Re: Z80 MC testing

 

I don't know,? I will need some time to set up and test here.



On Friday, April 4, 2025 at 12:09:14 a.m. EDT, Kerem Kapkin via groups.io <kkapkin@...> wrote:


When I use the instructions on page 24, Examine Input Port, Press 5 12, read in12 78, instead I am getting blinking FF. Is this normal? Does this indicate in have an HW problem?
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