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To add to this a bit, assume that the loss of power is unpredictable. The Z80 needs to know when a power loss occurs in order to be able to “save state” (i.e. the registers, etc.). The z80 has a non-maskable interrupt that could be triggered by the power loss through another circuit. The NMI vector would point to the save state code. But then, how long do you have to save the state?? You’d need to figure out how long it takes for the power to drop to a point where the chips stop operating (let’s say that’s 4.8v), but that timing depends on power consumption and supply voltage.? Then you can calculate how many instructions can execute in that time period, and hopefully that’s enough to save the CPU and hardware state. At 4mhz, the instructions take anywhere between 1us and about 6us. So, its “just math” so to speak.? On power-up, you’d check a flag to see if the state was successfully saved and either re-load it or start fresh.? NVRAM supervisory chips can sense the power fail and trigger the interrupt. I have?not tried this, but that’s the theory on how it could work but as Allison said, it’s both a software and hardware solution.? Rich On Thu, Apr 10, 2025 at 17:09 ajparent1/kb1gmx via <kb1gmx=[email protected]> wrote:
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