Re: Strange behavior of #8 button
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Thanks Lee, a 22K resistor in parallel with R4 A between pins 1 and 2 solved the problem with S8.
Kerem Kapkin wrote:
> Here is the recommended setup for standalone testing of the front panel...
> J2 Pin 9 [/out] connected to 3 components. 0.1uF cap other end ground,
> momentary switch other end ground,
> 100K resistor other end Vcc(5V).
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Correct. This provides a debounced pushbutton to clock counter U2A.
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> J2 Pin 24 -CLOCK- high (Vcc) or low (Ground)
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Either is fine; you just don't want to leave a CMOS input floating.
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> P1 pin 1 ground to (-) power supply
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Or J2 pin 10 also works.
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> J2 Pin 19 Vcc to +5V power supply
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With this setup, you can step counter U2A through its states 0-7. Each state is output on J2 pins 11, 12, and 13. Each state should set the corresponding output of U3 low so you can test each button.
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I think I see the problem with the "8" key! When U3 output C0 is low, IN4 (J2 pin 15) should be high. But transistor Q3 is also connected to C0. It is a "pre-biased" FJN3305, which has internal 10k and 4.7k resistors between its base and emitter. Its emitter ties to C0, and its base to R1D, a 1.5K to ground.These three resistors (10K + 4.7K + 1.5K = 16.2K) are pulling C0 low despite 18K R4A trying to pull it high! Thus the "halfway between" logic level, on IN4.
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I'm busy preparing for VCF-East right now, but will confirm this when I return. In the meantime, I'll bet putting a lower value resistor (like 1.5K) in parallel between R4A pins 1-2 will fix the problem.
Lee
--
Excellence does not require perfection. -- Henry James
But it *does* require attention to detail! -- Lee Hart
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Lee A. Hart
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Kerem Kapkin