John,

if you wanna give it a shot in real world lab test I can gladly mail you a pcb and a pair of FDT86256. I have couple of spare boards.

73

Barb WB2CBA

Some more simulation notes on this...

The model parameter that establishes the drain breakdown voltage is called Ebreak, and is set at 160.5V. Device specification is 150V. The device datasheet claims an ability to absorb single pulse avalanche events up to 1mJ energy.

The drain current transitions are very sharp, sub 5 nSec rise and fall. This is very jarring to the rest of the system, producing copious ringing. The ringing appears to stem from transformer leakage inductance combining with parasitic drain capacitance, or when the transformer is set to ideal coupling, reactive returns from the LPF will allow such ringing. The drain voltage and current ringing does not appear to damage output power production, but it is certainly messy. Setting up an ideal output transformer coupling into a purely resistive load kills off all the ringing, confirming the above.

When running in current-fed mode (ie. without the 100nF capacitor at transformer CT), the voltage at the transformer CT is jerked around wildly, swinging from 6V to 30V. Output power is reduced.

JZ

On Sat, Sep 23, 2023 at 5:12?AM John Zbrozek <jdzbrozek@...> wrote:

Hi Ross,

I played with this a bit more this morning.

To answer your question about the sim of the transformer, at the moment I simply use three coupled inductors with K=1. Nothing fancy.

Some additional comments from my dabbling this AM:

The current-fed mode for this amplifier runs with all?kinds of odd behaviors. Not the least is an EOT spike that hits 160 volts and a hard limit there that looks like breakdown. I haven't yet spotted what in the model sets the breakdown point.

I get much better results running these devices in voltage-fed mode, using a 100nF capacitor at the CT of the output transformer. No spike, all waveforms are cleaner, higher output power. Still SMH about that. Optimizing the transformer ratio remains TBD.

The Vth of the model is currently set at 3.85 volts. With a 5V supply tied to the driver chip models, a drive up level of only 4.6 volts is obtained. This is a bit low for driving this transistor. Turning up the logic supply to 6V produces a much more satisfying result and substantially improves the drain voltage down-level and the output power. This is not practical, of course, but serves to illustrate one issue with the use of these transistors.

More later. There is still much to be explored.

JZ

On Sat, Sep 23, 2023 at 4:12?AM Afghan Kabulldust via <kabulldust=[email protected]> wrote:

Tony and JZ,

What transformer model are you using in the LTSpice sim of the PA? WTST of RWTST? That is a picture of your .asc?

73

Ross

6

On 23 Sep 2023, at 06:59, HA3HZ <gyula@...> wrote:

?

? Like More ?

John Z 12:09am ? #110672?? I have run it, Tony, but it is still too early to say much. Two of these seem to produce a bit more output power than 4 BS170 in a 20m sim, but the drain currents I see are transitioning sharply and ringing wildly. I will play more with it later. ? JZ

In connection with another experiment, I noticed F5NPV Didier's experiences. Didier applied ES5DOL's suggestion to a Fetes power stage.
He inserted a 0.1...1Ohm and a 220nF capacitor parallel to it between the FET Source and the ground.
With this solution, you replaced the RC elements between Gate and Drain. The latter are meant to stop the ringing.
Perhaps it would be worth looking at this possibility here as well.
Just a small suggestion.
--
Gyula HA3HZ

Hi Ross,

I played with this a bit more this morning.

To answer your question about the sim of the transformer, at the moment I simply use three coupled inductors with K=1. Nothing fancy.

Some additional comments from my dabbling this AM:

The current-fed mode for this amplifier runs with all?kinds of odd behaviors. Not the least is an EOT spike that hits 160 volts and a hard limit there that looks like breakdown. I haven't yet spotted what in the model sets the breakdown point.

I get much better results running these devices in voltage-fed mode, using a 100nF capacitor at the CT of the output transformer. No spike, all waveforms are cleaner, higher output power. Still SMH about that. Optimizing the transformer ratio remains TBD.

The Vth of the model is currently set at 3.85 volts. With a 5V supply tied to the driver chip models, a drive up level of only 4.6 volts is obtained. This is a bit low for driving this transistor. Turning up the logic supply to 6V produces a much more satisfying result and substantially improves the drain voltage down-level and the output power. This is not practical, of course, but serves to illustrate one issue with the use of these transistors.

More later. There is still much to be explored.

JZ

On Sat, Sep 23, 2023 at 4:12?AM Afghan Kabulldust via <kabulldust=[email protected]> wrote:

Tony and JZ,

What transformer model are you using in the LTSpice sim of the PA? WTST of RWTST? That is a picture of your .asc?

73

Ross

6

On 23 Sep 2023, at 06:59, HA3HZ <gyula@...> wrote:

?

? Like More ?

John Z 12:09am ? #110672?? I have run it, Tony, but it is still too early to say much. Two of these seem to produce a bit more output power than 4 BS170 in a 20m sim, but the drain currents I see are transitioning sharply and ringing wildly. I will play more with it later. ? JZ

In connection with another experiment, I noticed F5NPV Didier's experiences. Didier applied ES5DOL's suggestion to a Fetes power stage.
He inserted a 0.1...1Ohm and a 220nF capacitor parallel to it between the FET Source and the ground.
With this solution, you replaced the RC elements between Gate and Drain. The latter are meant to stop the ringing.
Perhaps it would be worth looking at this possibility here as well.
Just a small suggestion.
--
Gyula HA3HZ