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Gordon Kennedy
Interesting about the re-application of power to get the unit to start- I recently had a PIC based project that had the same start up problem and I discovered that I had to switch from a regular 7805 in the power supply?to a LDO version and never had an issue with the 30 units that?were built.
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73, Gord
VE3GKN
From: cctbcn
To: QRPLabs@... Sent: Wednesday, October 10, 2012 10:59:46 AM Subject: [QRPLabs] Inconsistent timing in WSPR mode ?
I've put my 30 meter UQRSS together and have been fiddling with it for a bit now and have noticed something that has me scratching my head. I'm using a Axiom Sandpiper II GPS module that has a serial output (RS-232, which I have inverted to 5 volt logic) and a 1pps output that goes high (to +3.3 volts) for 100 milliseconds. The GPS receiver outputs a number of sentences, namely the GGA, GLL, GSV, GSA, RMC and VTG strings: There doesn't appear to be any way to select which ones are emitted. What I'm observing is that timing of the clock displayed in WSPR mode seems to vary randomly +/- 1 or 2 seconds from actual GPS time and WWV. What is interesting is that the second displayed on the LCD *is* synchronized precisely with UTC - it's just that it's the wrong second. I've tried baud rates from 4800 through 38400 and haven't been able to see any difference. Thinking that the 100ms long 1pps pulse (rising edge coincides with the second) I put a series capacitor (0.05uF) with a 10k to ground on the UQRSS side to turn it into a brief rising pulse, but this hasn't changed anything, either. One thing that I *do* see happening is that if I stare at the display long enough, I note that the seconds digits occasionally do not advance which explains it occasional lagging: Apparently, it will eventually re-check the time and, unseen by me thusfar, it will pop ahead again - by 1 or 2 seconds in advance of UTC. So, several questions come to mind: - Is the 1pps rising-edge sensitive? If so, this would make its duration irrelevant. - Is the logic threshold on the 1PPS input safely within the range to accommodate 3.3 volt logic? - Could too many NMEA sentences be doing something internally (e.g. too many recources/interrupts) that might cause the timing to wander excessively? Since the 30 meter oscillator is on all of the time, I suppose that I could monitor the frequency during the "key up" period if I knew the amount of offset and if there is any repeated self calibration going on - this, to see if the FLL is functioning, or also being affected by the loss of 1pps pulses? * * * On an unrelated note, I have observed that occasionally, the CPU (or possibly the display) does not start up when power is applied, but a disconnecting and re-application of power has always been successful. The recent thread about popped finals brings this to mind: If the oscillator doesn't start up for some reason - and neither does the CPU - then the FET could be turned fully on with no RF drive if the pin were to float high - or even if the CPU was running, but the oscillator outputting a logic state that, when keyed, turned on the FET. Years ago, I designed a LowFER/MedFER power amplifier that used a coupling cap, resistor and diode to protect the FET should a similar event occur! 73, Clint KA7OEI |
