I'm interested in doing some SDR tinkering, using the receiver module kit and the VFO kit.? The LO input on the receiver module is divided down by 4 to make the quadrature clocks for the Tayloe mixer.? Could I, alternatively, program CLK0 and CLK1 on the Si5351A to make the quadrature clocks, disconnect the 2-bit counter, and route the two clock signals directly to the multiplexer chip?? Might that enable me to increase the bandwidth of the receiver, assuming I create an appropriate bandpass filter to go ahead of the multiplexer?
?
Thanks,
Eric
