Dear All,

As Alwyn says: "What really annoys me is the lack of support of equipment which uses older versions of Windows- knowing the policies of that company, I now insist on hearing how long term support will be assured before I buy."

Indeed!!!

I have a Tek TDS7000B series in our group that I am trying to "repair" because its Windows 2000 OS has gone AWOL from a hard drive failure. Tek refuse to supply the Microsoft Windows restore discs "because of licensing issues" which to me seems entity bogus for a piece of equipment that cost well over GBP20,000 in 2003 (i.e. more than a Hi-End VW Golf Turbo).

We have happenchance found an original Restore Manual and set of discs on e$ay which fingers crossed will resolve the issue, but the lack of support from Tek is astounding for such expensive equipment (TDS7154B).

I am now recommanding Pico Technology scopes wherever possible, even though I personally prefer a 'scope with knobs on it the price differentials are to great to ignore.

Best,
Susan.

Susan Parker, Laser Consortium, Department of Physics, Imperial College London, UK.

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On 7/25/2019 3:50 PM, saipan59 wrote:

I want to suggest that the discussion should include the trade-offs of an FPGA implementation vs an MCU [I have very limited experience with the former, but a lot with the latter], as it relates to the applications we're talking about.

I'll weigh in here.

FPGA:? lots faster, more expensive, extensive I/O.? True hardware implementation, simultaneous operation of functions.? Often 3.3 volts for I/O.? Cost (including CPLDS, which are more limited in scope, cheaper, and generally nonvolatile), will run from about 2 dollars to 16 dollars for Xilinx parts (what I'm familiar with).? VHDL is essentially specifying hardware.? If you want it to respond to different conditions (as in pretending to have a program in it) then? you need either a state machine or a processor IP (Picoblaze is possible).? RAM resources are somewhat limited depending on chip (CPLDs have none).? Best use: smart hardware and hardware subsystems.? SPI interface may be programmed in for processor interface.? Programming is in VHDL or Verilog.?

Microprocessor:? No hardware systems need to be designed.? Programming is sequential, slower, although DMA and some subsystems can operate independently.? 3.3 and 5.0 volts depending on processor.? Cost may run from less than one dollar to 20 dollars depending on family and manufacturer.? Microprocessors need external memory, external I/O subsystems.? Microcontrollers take program and data memory inside, and provide subsystems (I2C, SPI, Serial, etc.).? Programming is in any high level language available or assembly.? Operating system can give illusion of simultaneous operation, but unless more than one processor core is available, operation is time shared.

I'll add some points about FPGAs:

• short latency and guaranteed latency between input and/or signals changing, i.e. hard realtime operation. The operations are performed directly by hardware, so there are no interrupt service routines, multitasking etc to "get in the way"
• Xylinx Zync devices have lots of FPGA fabric plus two onboard very capable ARM A9 processors. The processors can run an RTOS or Linux, or RTOS+Linux. This allows tight integration between the processor and custom hardware

There is one processor that is half-way between a standard MCU and FPGA in terms of performance: the XMOS xCORE devices, available from Digikey. They have a long and solid pedigree, being directly descended from Transputers and Occam and Hoare's Communicating Sequential Processes (CSP) formalism.

A single chip can have up to 32 cores (expandable with chips), run at 4000MIPS, have onboard RAM and flash memory, "FPGA like" IO (e.g. SERDES etc)? - but that is useless unless you can program them quickly and effectively. The xC language enables that, being designed for multiprocessing from the ground up - unlike C. This makes it surprisingly easy and fun to actually use the devices.

As for hard realtime, the IDE will guarantee the execution times and latency. That avoids the need to run the code, make measurements, and piously hope you have stumbled across worst-case execution times. An example is that you can use some of the cores to directly grab and process 100Mb/s serial data from an ethernet or USB interface, while other cores simultaneously get on with the real work.

Yes, I'm a fan of them, for the right application.

Altera was purchased by Intel, so Oracle might have more luck if they wanted to try again.

Xilinx requires a license for their free edition, 1 year long as I recall, which always seems to expire in the middle of a hot project and have to pause to wait for renewal.

Intel offers the Quartus software in 3 versions, Intel Quartus Prime Lite Edition as a free download with no license file required, now up to version 19.1, and Prime Standard and Prime Pro as paid versions.

Xilinx has several different programming modes, so the learning curve to get from compiled VHDL or Verilog code to a programmed part seems so much simpler with Altera.

I also like that the Altera Max 2 parts I use EPM240-EMP1270 don't require a separate memory chip to store the bit map, although that's not a problem if using one of the Chinese FPGA complete modules.

What sort of processing needs to occur in the FPGA? With each different hardware adapter requiring a different driver, and only talking to different software, It's not as simple as simply converting from the serial USB data stream to parallel HPIB.

John

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Well, I don't have a problem with that, but I'm just a contributor to the thread.

I have a lot (~43 years) experience with both embedded hardware (including large FPGA designs) and embedded software, as well as embedded system architecture, so I'll add my $.02.

Partitioning an architecture into the hardware and software components is not always easy (in fact, it almost always is not easy).

Remember that, at 70,000 ft., and ignoring all of the development methodology issues, an FPGA or other fixed-hardware portion of a design is different topologically than the part that the processor handles. For example, the FPGA design is fixed, topologically and (ignoring re-programming with different images for different applications) may be designed to be deterministic in it's behavior. Aside from design faults that cause timing and metastability issues. A schematic or other fixed-topological view of the hardware is the only model needed to depict the hardware (deciphering it is another issue).

The processor-controlled portion of the design necessarily involves the execution of code, which has no fixed topology at run-time, and is not necessarily deterministic. A software based design requires, at a minimum, both a structural model of the code and a behavioral model (think UML or SysML) to understand.

It is not necessary to have both elements in an embedded system, but many embedded systems do have both.

My point is that the determination of whether to use an FPGA or other fixed-hardware design, or a processor-based design, or a combination of both, is entirely dependent on the requirements that dictate how the system behaves and what it is supposed to do. In the commercial world, that determination also must take into account fixed production costs and maintenance costs of the system.

Most (?) very small embedded systems designed by "hobbyists" today use a single SBC such as an Arduino, Raspberry Pi, BeagleBone, etc.and there is no need for the amount of fixed hardware that would make a CPLD or FPGA a reasonable design option, But, as the GPIB-USB discussion shows, sometimes maybe using both is a good idea.

Hmmm, well, I may have transgressed "simple".? LED controller (pulse, pwm brightness), timer and trigger for ultrasonic distance measurement, Neopixel encoder, SPI interface, programmable pins, FIFO, usart, I2C to parallel decoder (in the works).

also GPIB encoder, replacement for an 8259 keyboard/led driver, and support circuitry for a DM5010.?

Harvey

DaveD

On 7/25/2019 3:50 PM, saipan59 wrote:

I want to suggest that the discussion should include the trade-offs of an FPGA implementation vs an MCU [I have very limited experience with the former, but a lot with the latter], as it relates to the applications we're talking about.

Anecdote: When designing the 'Power-On Reset' features for a product a few years ago, I planned to use a small MCU. When the Architect found out, he vetoed it, saying "We can't rely on running code for a critical start-up function". He was fine with an FPGA or CPLD (at higher cost, more board real estate, less flexible behaviors, and HUGE complexity in the 'code' that runs under the covers). My belief is that he was equating an FPGA to the old bipolar PAL's used in the 70's/80's, where logic functions were literally burned in, so it was considered super-reliable.
In the end, I was able to meet the requirements with just a few little timer (1-shot) chips and a bit of glue logic.

Pete

Virus-free.

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I want to suggest that the discussion should include the trade-offs of an FPGA implementation vs an MCU [I have very limited experience with the former, but a lot with the latter], as it relates to the applications we're talking about.

I'll weigh in here.

FPGA:? lots faster, more expensive, extensive I/O.? True hardware implementation, simultaneous operation of functions.? Often 3.3 volts for I/O.? Cost (including CPLDS, which are more limited in scope, cheaper, and generally nonvolatile), will run from about 2 dollars to 16 dollars for Xilinx parts (what I'm familiar with).? VHDL is essentially specifying hardware.? If you want it to respond to different conditions (as in pretending to have a program in it) then? you need either a state machine or a processor IP (Picoblaze is possible).? RAM resources are somewhat limited depending on chip (CPLDs have none).? Best use: smart hardware and hardware subsystems.? SPI interface may be programmed in for processor interface.? Programming is in VHDL or Verilog.?

Microprocessor:? No hardware systems need to be designed.? Programming is sequential, slower, although DMA and some subsystems can operate independently.? 3.3 and 5.0 volts depending on processor.? Cost may run from less than one dollar to 20 dollars depending on family and manufacturer.? Microprocessors need external memory, external I/O subsystems.? Microcontrollers take program and data memory inside, and provide subsystems (I2C, SPI, Serial, etc.).? Programming is in any high level language available or assembly.? Operating system can give illusion of simultaneous operation, but unless more than one processor core is available, operation is time shared.

.

Anecdote: When designing the 'Power-On Reset' features for a product a few years ago, I planned to use a small MCU. When the Architect found out, he vetoed it, saying "We can't rely on running code for a critical start-up function".

Note to architect, it's been done in military qualified systems for quite a few years.? Tektronix (and others) had extensive processor diagnostics before the horse was allowed outside the barn.

He was fine with an FPGA or CPLD (at higher cost, more board real estate, less flexible behaviors, and HUGE complexity in the 'code' that runs under the covers). My belief is that he was equating an FPGA to the old bipolar PAL's used in the 70's/80's, where logic functions were literally burned in, so it was considered super-reliable.

And he may have been thinking of early microprocessors as well.

Harvey

In the end, I was able to meet the requirements with just a few little timer (1-shot) chips and a bit of glue logic.

Pete

On 7/25/2019 10:58 AM, Dave Daniel wrote:

Also, don’t foget issues of cost of buying and/or finding “free” Verilog/VHDL copiler/synthesis and simulation tools.

ISE webpack is the free edition.? All it wants to do is phone home to mommy to tell them what kind of device you're using.? No worse than Microsoft or symantec.

simulator, editor, fitter, programming software, pin planner, etc.

Good for the larger projects.

Harvey

DaveD

Sent from a small flat thingy

On Jul 25, 2019, at 10:08, Harvey White <madyn@...> wrote:

On 7/25/2019 12:58 AM, John kolb wrote:

CPLD's are less complex than FPGA's but not necessarily cheaper as the newer design parts get a lot more logic in a lot less silicon, at the cost of using lower voltages.

Xilinx. 32 cell = 1.50, 64 cell = 3.25, 128 cell = 7.00, 256 cell = 15 dollars

Spartan 3AN (built in eeprom) 50K gates, about 14 dollars.

Spartan 6, (no eeprom, use winbond = 0.75) about 12 dollars, well over 50 K gates, has a 16 dollar pin compatible version with twice capacity.

Have standardized on the Spartan 6.

Pay careful attention to the bypass capacitors and clock run out to the configuration eeprom. Programmer available through amazon, web edition (local compile, report back to daddy) is free.

3.3 volts but then again was using them with Xmega and now with ARM.

All chips in non-BGA versions, TQFP-144, so therefore solderable.

SPI interface available through open cores, suggest register structure with read/write registers and go from there.

(and yes, done that....)

Harvey

Lattice 7000S series parts were good for a 5V part, but no longer available new, although still plenty on ebay.

An Altera Max 2 series part (3.3V), mounted on a PC board along with a clock oscillator and 5V to 3.3V voltage regulator would be a good start.
EPM240 series along with a USB Blaster programmer for about $12


Similar modules are available for other CPLDs and FPGAs if the logic doesn't fit the EPM240.

Using a premade module gets one away from having to deal with surface mount parts, at least as long as the interface IC's are still available as thru-hole parts.

I'm still hoping I can figure out how to use the UGPlus to talk to my HP 3456.

John

On 7/24/2019 1:12 PM, Harvey White wrote:

On 7/24/2019 2:01 PM, saipan59 wrote:

I once did a design that had the upD7210 in it (includes controller), driven by an XMEGA. I've got a similar design (unproven yet) that is driven by an ARM processor. Since the 75160/75162 are readily available (or at least, were....) I'd stick with them. I also have a possibility of using an FPGA to do the same. I'd stick with the FPGA for a new design since it can always be tweaked. I suspect that a CPLD may be too expensive for the complexity needed at that level.

FPGA goes through level shifters to the 488 bus drivers, so it's all well protected.

After I do a bunch of software (OS/graphics redesign) that's on the list (it says here......)

Harvey

I've been watching this thread with interest, and the group as a whole has identified most of the issues I dealt with in developing KISS-488. I did in fact use a PIC microcontroller with the high-current drivers on the pins going out to the bus (with series protection resistors). I also realized that the standard GPIB terminators are the Thevinin equivalent of 2K to 3.3V. Downright convenient using a modern 3.3V power supply for all the logic, and 3.3V is well above the standard TTL threshold of 2.4V for a logic high.

That said, I'm sure many on this list are dyed-in-the-wool hackers (in the older and more respectful sense of the word), and would enjoy the challenge of building your own. But if you just want to be able to get a screen dump, or log data via Telnet, or just run your instrument from a PC, please give KISS-488 a look.

Steve Hendrix

I've been meaning to read into the difference between the protocols of the SCSI PATA adapters for CD-ROM drives and hard drives since I see there are on the market adapters that are more cost effective for those devices.?

Wondering and thinking that there is some sort of firmware modification to enable... otherwise I guess some other circuit with chip is required.?

Guessing is just a firmware mod however there might be something more complex with the linked list data structure of read/write protocol and needing a SOIC.

- James Finch?

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Well, I don't have a problem with that, but I'm just a contributor to the thread.

I have a lot (~43 years) experience with both embedded hardware (including large FPGA designs) and embedded software, as well as embedded system architecture, so I'll add my $.02.

Partitioning an architecture into the hardware and software components is not always easy (in fact, it almost always is not easy).

Remember that, at 70,000 ft., and ignoring all of the development methodology issues, an FPGA or other fixed-hardware portion of a design is different topologically than the part that the processor handles. For example, the FPGA design is fixed, topologically and (ignoring re-programming with different images for different applications) may be designed to be deterministic in it's behavior. Aside from design faults that cause timing and metastability issues. A schematic or other fixed-topological view of the hardware is the only model needed to depict the hardware (deciphering it is another issue).

The processor-controlled portion of the design necessarily involves the execution of code, which has no fixed topology at run-time, and is not necessarily deterministic. A software based design requires, at a minimum, both a structural model of the code and a behavioral model (think UML or SysML) to understand.

It is not necessary to have both elements in an embedded system, but many embedded systems do have both.

My point is that the determination of whether to use an FPGA or other fixed-hardware design, or a processor-based design, or a combination of both, is entirely dependent on the requirements that dictate how the system behaves and what it is supposed to do. In the commercial world, that determination also must take into account fixed production costs and maintenance costs of the system.

Most (?) very small embedded systems designed by "hobbyists" today use a single SBC such as an Arduino, Raspberry Pi, BeagleBone, etc.and there is no need for the amount of fixed hardware that would make a CPLD or FPGA a reasonable design option, But, as the GPIB-USB discussion shows, sometimes maybe using both is a good idea.

DaveD

I want to suggest that the discussion should include the trade-offs of an FPGA implementation vs an MCU [I have very limited experience with the former, but a lot with the latter], as it relates to the applications we're talking about.

Anecdote: When designing the 'Power-On Reset' features for a product a few years ago, I planned to use a small MCU. When the Architect found out, he vetoed it, saying "We can't rely on running code for a critical start-up function". He was fine with an FPGA or CPLD (at higher cost, more board real estate, less flexible behaviors, and HUGE complexity in the 'code' that runs under the covers). My belief is that he was equating an FPGA to the old bipolar PAL's used in the 70's/80's, where logic functions were literally burned in, so it was considered super-reliable.
In the end, I was able to meet the requirements with just a few little timer (1-shot) chips and a bit of glue logic.

Pete

I want to suggest that the discussion should include the trade-offs of an FPGA implementation vs an MCU [I have very limited experience with the former, but a lot with the latter], as it relates to the applications we're talking about.

Anecdote: When designing the 'Power-On Reset' features for a product a few years ago, I planned to use a small MCU. When the Architect found out, he vetoed it, saying "We can't rely on running code for a critical start-up function". He was fine with an FPGA or CPLD (at higher cost, more board real estate, less flexible behaviors, and HUGE complexity in the 'code' that runs under the covers). My belief is that he was equating an FPGA to the old bipolar PAL's used in the 70's/80's, where logic functions were literally burned in, so it was considered super-reliable.
In the end, I was able to meet the requirements with just a few little timer (1-shot) chips and a bit of glue logic.

Pete

Me either. Next step is sealed boxes with "No user replaceable parts" When it breaks toss it and buy a new one.
Really dumb policy.

On 7/25/2019 12:09 PM, Daun Yeagley wrote:

Hmm.... looks to me like they just signed their death certificate.
Very sad to see this, but I guess not surprising.? Definitely NOT the company I used to work for.?? :-(
Daun
Daun E. Yeagley II, N8ASB

WB6KBL

If I had serial #1 of something interesting, I would consider donating it to an appropriate museum collection.

Pete

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This will reduce the value of their equipment as it will increase the lifecycle costs. Many, many companies rely on local third party firms for cal and repair so make equipment more budget friendly.?

On 7/25/19 2:58 PM, Caesar Valenti wrote:

I see that Keysight is now going to go the route of not providing any
service adjustments on future products and of not providing any repair
parts. The exception, of course, is to our own service centers.? They
want to eliminate any 3rd party repair/cal facilities so that Keysight
will get the money instead.? Supposedly, this is to ensure high quality
repair/calibrations.? Of course, this tends to prevent any hobbyist from
doing their own repair and any Keysight repair will probably be
outrageously expensive for any non-corporate entities.?

We have already been instructed to remove all adjustments from our line
of network analyzers.? We said no...(actually, hell no!)? Fortunately,
our manager backed us up on this for now, but it is just a matter of
time before this becomes standard Keysight policy on *all* instruments.?
I don't think Bill and Dave would approve of this strategy, but it is
very hard to get their current opinion or get them involved!? I can see
it may soon be time to retire.

It sounds like Keysight's upper management has forgotten the nature of
the business that they're in, and the nature of their own company.
Suits often forget (or want to erase) where things come from.

All good things must come to an end. If/when they go through with
this, it will be the end of their test equipment business. Of course
they'll blame something else, and the suits who made the decision will
be out with their golden parachutes before the shit hits the fan.

-Dave

--
Dave McGuire, AK4HZ
New Kensington, PA

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Hmm.... looks to me like they just signed their death certificate.

Very sad to see this, but I guess not surprising.? Definitely NOT the company I used to work for.?? :-(

Daun

I see that Keysight is now going to go the route of not providing any service adjustments on future products and of not providing any repair parts. The exception, of course, is to our own service centers.? They want to eliminate any 3rd party repair/cal facilities so that Keysight will get the money instead.? Supposedly, this is to ensure high quality repair/calibrations.? Of course, this tends to prevent any hobbyist from doing their own repair and any Keysight repair will probably be outrageously expensive for any non-corporate entities.?

We have already been instructed to remove all adjustments from our line of network analyzers.? We said no...(actually, hell no!)? Fortunately, our manager backed us up on this for now, but it is just a matter of time before this becomes standard Keysight policy on all instruments.? I don't think Bill and Dave would approve of this strategy, but it is very hard to get their current opinion or get them involved!? I can see it may soon be time to retire.

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I'm starting anew thread for the FPGA development discussion that veered off from the OSSW/OSHW AR488 GPIB-USB adapter discussion.

Responding to Dave_G0WBX's comment, what development tools are available for the creation synthesis and simulation of code for the Altera parts?

We stopped using Altera parts at Oracle a while back because the Oracle and Altera legal departments could not agree on a contract. Even though we had several very large Altera designs in production.

DaveD

Addendum: I'm also pretty certain there is at least one bad germanium transistor (maybe Q109) in the 10 KC amplifier/oscillator circuits. The manual indicates that the waveform should be sinusoidal with some crossover distortion...and it's pretty much anything but sinusoidal. It goes crazy when the range is switched out of null too.

Sean

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We need to move the FOGA development discussion to a new thread.

DaveD