Thank you. All this helps me piece together how the setup works. Right now I am collecting data and once it starts forming a coherent picture I will post it.?
The firmware plays a big part in this as well. For example, after default pretune values are set, test 48 creates individualized pretune values for that specific instrument. There is only so far that can compensate, though, and that¡¯s apparently what I¡¯m running into. ?What I don¡¯t yet know is whether the problem is on that board or if the YIG oscillator has drifted out of spec. It would be helpful to know just how far that firmware can compensate. I do see that my analog bus voltages are spot on, and seeing how your pretune voltage waveform is lower than mine, I still suspect a problem on my phase lock board. I have verified that the voltage to current converter is operating properly, and since the measurement resistor is verified well within its 1% tolerance, that the current through the YTO main coil should thus be within design tolerance as compared to the 1V/GHz signal. Thus any inability to be lower in voltage would have to be in the DAC, reference, voltage shift area that feeds the V/I converter. If however the replacement phase lock board has the exact same behavior I would have to look again at the YIG oscillator.?
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On Mar 20, 2019, at 11:17 PM, pianovt via Groups.Io <
pianovt@...> wrote:
Hi Peter,
The main and FM coil signals pass through the A3 ALC board like this:
<dummyfile.0.part>
The FM -? tap to the cavity oscillator is not part of the basic phase lock scheme, it's a spur avoidance fix. You don't need to waste time on studying that unless the fault is there.
Since you mentioned that the YTO is off (high?) by 200MHz, I think you should look at the main coil driver. It seems like something is preventing the main coil driver from delivering a low current. I am not aware of a PLL switch point at 1 GHz, but I have forgotten a lot about it so I may be wrong.
Vladan
