Hello,
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I'm trying to figure out some strange things with my 83630A synthesized sweeper.?
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I get fail on the following self tests:
A12 (SYTM Driver)
166 Offset DAC
167 Slope DAC
168 VComp summer
177 YTF Offset DAC
178 YTF Slope DAC
179 YTF VComp summer
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RF
269 LO Band locked check
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Sometimes, there are fails reported on A4 (Frac N) also, but currently not.
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Now that CLIPs are available there is a fair chance to fix this I hope.
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My problem, though, is that I can't see any problem in the output signal.?
Output power level is stable and harmonics seem to be suppressed over the complete frequency range -> A12 seems to be operating.
I can measure a 100 MHz (LO band?) signal at correct frequency and level -> LO band locked?.
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Looking at the schematics, it seems like the signal VCOMP is passed to the Analog bus (Q in the schematic for A12), which should enable testing of these signals.?
It seems a little unlikely that both DACs on A12 (U23/B and U9/D) should break at the same time while still enabling 'full' functionality??
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Suspecting the ADC section on the CPU board (N), I tried to connect to TP12 (MUX OUT) only to find that loop at the top of the board was cut away and the trace leading to U58 (OP AMP before ADC) was cut and sealed - really making sure TP12 would be inaccessible. The edge of the board was marked with blue paint in this area also.
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Anyone has a clue why TP12 should not be accessible (looks like fix from the factory) or even has the same board and fix (08360-60215)?
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Any comments on the fails would also be very much appreciated.?
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Any details about what the different self tests really do would be very interesting to know.
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Regards,
? Staffan??
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