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Re: HP-8753E Test Fixture Offset Value


 

Seems interesting result - I would have expected the open to be more problematic because of fringing. Any idea as to what was actually going on?

Cheers!

Bruce

Quoting Lothar baier <Lothar@...>:

I never quantified it , normally for on Wafer calibration to the probe tip the short standard is nothing but a shorting bar on the substrate but for offset shorts it becomes a different story .
When I did characterization for GaN devices both LP and S-parameter the recticles had short and open reflect standards and there was a consistent and repeatable difference in results and we were adviced upon completed data review not to use the short !

-----Original Message-----
From: [email protected] <[email protected]> On Behalf Of Bruce via groups.io
Sent: Wednesday, April 13, 2022 3:18 PM
To: [email protected]
Subject: Re: [HP-Agilent-Keysight-equipment] HP-8753E Test Fixture Offset Value

Lothar -
Interesting. For the case of vias are not being required, how much difference in accuracy between short and open (assuming optimal design of the test board) do you observe as a function of frequency ??

Cheers!

Bruce

Quoting Lothar baier <Lothar@...>:

Generally whether to use open or short depends on the
fixture/application , for mechanical fixtures like ICM a short is
often easier to realize and as David pointed out better but for test
boards or on wafer measurements I found the use of a open to yield
more accurate results especially at higher frequencies , the problem
here is that in those apps a short requires the use of vias which adds
inductance

From: [email protected]
<[email protected]> On Behalf Of Rich Miller via
groups.io
Sent: Wednesday, April 13, 2022 8:43 AM
To: [email protected]
Subject: Re: [HP-Agilent-Keysight-equipment] HP-8753E Test Fixture
Offset Value

Thanks for this information, I think it¡¯s pointing me in the right
direction. I will also review the application note Lothar sent over.
There is a whole section on TRL, but I had not correlated TRL to this
application in my mind.

The application is low UHF, and I would be ok if my total accuracy
displayed was +/- .5dB. I simply was trying to avoid having to look at
the instrument and then account for the fixture loss. The fixture is
about flat and consistent in the frequency ranges I am currently
working with. There is almost no noticeable deviation across the DUT¡¯s
B/W (it¡¯s in the .1 dB range).

While I am using the real numbers in Excel, I could easily get away
with simply having the analyzer calculate out the 40dB loss of my
fixture for this application. While I understand this may be a
acceptable practice for this DUT, it will not be for others I work
with, which would be around L-Band, because of the high degree of
variation in the frequency response of a fixture at those frequencies.

Rich



On Apr 13, 2022, at 6:48 AM, Dr. David Kirkby, Kirkby Microwave Ltd
<drkirkby@...<mailto:drkirkby@...>
wrote:
?
On Wed, 13 Apr 2022 at 03:58, Lothar baier
<Lothar@...<mailto:Lothar@...>> wrote:
disadvantage of TRL is that below 2GHz your delay lines become too
long so you have to go to SOLT which requires a Short , open , thru
and load the disadvantage of fixture boards is that you need to solder
the device down while fixtures usually clamp

Also, you really want a VNA with 2 reference receivers (4 receivers in
total), which the 8753E does not have. But it does have TRL*, which is
a sort of poor-man's TRL where the reference is sharted between the
two ports. But you need 6-10 dB attenuators on the ports so the
impedance remains relatively constant, despite internal switching in
the VNA. This reduces dynamic range.

I don't know the particular fixture, but it may be possible to put a
short where the DUT goes, then add a port extension until the phase is
180 degrees. If that's reasonably flat, and the magnitude of the
attenuation not excessive, then you can fairly easily do it on an
8753E. A short is better than an open, as a short has a phase of very
close to 180 degrees, whereas an open is not so close to 180 degrees
due to the fringing capacitance.

Dave












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