Re: Scoping the Power Rails [8566B]
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I have not read this thread so this might have been addressed already but have you checked ripple on your supply voltages for the PLL ?? a PLL essentially phase locks a VCO or YTO to a reference frequency ,? if the DC voltage the tuning
voltage is derived from has excessive ripple than this translates on the tuning voltage which ¡°modulates¡± the VCO and in turn prevent the VCO from locking !
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From: [email protected] < [email protected]>
On Behalf Of Jinxie via groups.io
Sent: Thursday, March 10, 2022 3:16 AM
To: [email protected]
Subject: Re: [HP-Agilent-Keysight-equipment] Scoping the Power Rails [8566B]
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Bruce, I think you may have missed the test I did that showed whilst PLL1 and PLL3 are locked (as evidenced by their green LEDs) PLL2 is
not (as evidence by the voltage on the HUL2 test point on the A10A6 board being non-zero ( and *highly* unstable, in fact).
So I'm quite happy to do the tests you suggest WRT the YIG loop as they may provide extra clues, but must keep in mind the failure of PLL2 to lock.
There will now be the usual several hours delay whilst I go and earn a crust but I'll report back for further investigations later....
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