I made some verifications of the DAC in the Pretune-Circuit. Its U203 (labled 1826-1158), actually the DAC1218 from National Semiconductor.
It has a current output, translated to voltage in an opamp downstream.
I measured with FLL and PLL all disconnected from the module.
Fset=1030MHz -> VCO @ 920MHz, decreasing by approx 2 MHz during warmup.
Iout1: -1,5mV
Iout2: +0,5mV
GND: +0,5mV (ground level = power supply socket on IO-board)
VCC: +14,8V
Vref: 10,03V
Rfb: +6,73V
A1(MSB) - A12: 101010000000 low=0,1V, hi=3,7V -> decimal 2688
Fset=515MHz -> VCO @ 400MHz
Iout1: -0,9mV
Iout2: +0,5mV
GND: +0,5mV (ground level = power supply socket on IO-board)
VCC: +14,8V
Vref: 10,03V
Rfb: +0,653V
A1(MSB) - A12: 000100001100 low=0,1V, hi=3,7V -> decimal 268
According the patent mentioned by Matt the decimal values should be 324 and 3200 as min (515Mhz) and max (1030Hz) respectively.
That means the DAC is missing 56 steps at setpoint 515MHz and 512 steps at setpoint 1030MHz.
A step of 1 at the DAC should lead to an increase of approx. 180kHz (3200-324)/515.
The missing 512 steps at setpoint 1030 would account for 92MHz, if present that would give 1012 MHz, considerable closer to the setpoint.
The missing 56 steps at setpoint 515 would account for 10,1MHz, if present that would give 410 MHz, still quite far away from the setpoint.
Not sure what lesson to take here... to be contiued!a
At one time I was playing with the special functions. There was none that had an effect on the VCO frequency. But to my surprise the unit went into calibration after a power cycle... although half the connections are removed. It ended with error message pointing to the FastVCO. At least thats consistent...
cheers
Martin
Martin