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Using the tinySA to check the NEO-7M GSP locked output on spurs
The NEO-7M calims to be able to output GPS locked frequencies till 10MHz. But is this usable???
As measured using an external 30dB attenuator. Here is the 10MHz output 10MHz is there but 2,6 and 18MHz are -13.5, -15.5 and -9,5dB below the 10MHz so there seems to be a lot of jitter. could it be because a fractional divider is used to create 10MHz? The picture of 12MHz looks different, I assume because a divide by 4 from 48MHz is used so the only spurs you get is when the GPS lock pushes the 48MHz resulting in +/- 4MHz spurs Fairly clean, only a small amount of jitter. It seems even the 10Mhz is generated by a fractional divider from the internal 48MHz clock. All output frequencies that are not a divide by power of 2 from 48MHz suffer from the? fractional divider, even the 1MHz as can be seen below -- HBTE Files section:?/g/HBTE/files Erik, PD0EK |
There is some talk around other forums and with other experimenters that what you are saying is the case about jitter on the output.
Staying with even divisor ratio's gives the cleanest output, but I have seen various schemes to try and clean up the output where 10MHz is wanted. Most are not that successful. |
The NEO-7M has a dual modulus divider to deal with the non-integer ratio of 48/10.
It sometimes divides by one number, sometimes divides by a value one less than that number. This will almost certainly show up as phase noise on the Si4432 LO, how bad depends on the LPF used in the Si4432 PLL. Since it's designed for a 30mhz crystal oscillator, it probably wants a clean reference. I do think having the NEO-7M divide 48mhz by 8 to get 6mhz out, then multiplying by 5 should work, as per post #701.? A?GPS disciplined Si5351 should also work. The cheap 10 pin Si5351A wants a 25 or 27 mhz local oscillator, I hear that driving it with a 12mhz reference sort of works but is noisy. The Si5351C in the QFN20 is designed to take an external reference? at anywhere between 10mhz and 100mhz.? So one could drive the Si5351C reference with 12mhz directly from the NEO-7M, no need to discipline the Si5351C using firmware. Jerry, KE7ER? ? |
¿ªÔÆÌåÓýThere's a video here which shows the jitter clearly. Also, the way to program the output. vk3pe |
Does the NEO-7M work at all when dividing 48mhz by two, giving a clean 24mhz?
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Even if at a moderately low level? If so, the NEO-7M could drive a 24mhz reference into a cheap SI5351A directly, since 24mhz is not far from the reference it wants of 25 to 27 mhz. The Si5351 datasheet is here: ? ?? Section 5.6 on page 21 of the Si5351 datasheet "Applying a Reference Clock at XTAL Input" shows a 1 volt pk-pk clock capacitiviely coupled with 0.1uF into pin XA, pin XB a no-connect. This could be done on any of the common Si5351 proto boards, must first remove the crystal. This would be a very simple way to directly lock a $5 GPS timebase to an $5 Si5351A module. Previous solutions to this have rather complicated Si5351 firmware, which measures the? frequency of the incoming 1 pulse-per-second from the GPS and then slews the Si5351 correction factor to compensate.? ? Direct coupling avoids the slight errors this introduces, and allows most any Si5351 firmware to be used after recompiling for a 24mhz reference. Will work without recompiling if you can live with output frequencies that are always off by a ratio of 24/25 or 24/27, depending on the crystal frequency it was compiled for. Jerry, KE7ER On Sat, Jan 11, 2020 at 05:35 PM, Jerry Gaffke wrote:
The cheap 10 pin Si5351A wants a 25 or 27 mhz local oscillator, |
Si5351 can work with clocks far away from the 25-27Mhz range so lower clocks like 12MHz should not be an issue: On Sun, 12 Jan 2020 at 18:56, Jerry Gaffke via Groups.Io <jgaffke=[email protected]> wrote: Does the NEO-7M work at all when dividing 48mhz by two, giving a clean 24mhz? |
Dragan,
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Yes, the Si5351A sort of works outside the spec'd 25 or 27 mhz, as per post 704 > The cheap 10 pin Si5351A wants a 25 or 27 mhz local oscillator, > I hear that driving it with a 12mhz reference sort of works but is noisy. > The Si5351C in the QFN20 is designed to take an external reference? > at anywhere between 10mhz and 100mhz.?? Your reference is mostly pushing the reference frequency around until the Si5351 loses lock. He doesn't quantify how much jitter is unacceptable. He might well find the 10mhz reference out of the NEO-7m to be perfectly fine as a reference for his frequency counter, for example. But it would not be fine as a local oscillator in a receiver. How much of an issue the jitter would be at 10mhz, I'm not really sure. Here's my source, Hans of QRP-Labs: ? ??/g/qrptech/message/331 That entire discussion is worth a read. Hans was really pressing the edges on how far the VCO could go. And he found a very elegant way to create quadrature clocks from the Si5351. If the NEO-7M can create a clean 24mhz reference, that's ideal for driving an Si5351A. If it can't, then 12mhz followed by a doubler should be fairly easy to implement. Or 12mhz followed by an Si5351C. I am intrigued, it would be fun (and useful) to build a clean signal generator locked to a GPS. Jerry, KE7ER On Sun, Jan 12, 2020 at 10:14 AM, Dragan Milivojevic wrote:
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To be fair, while Hans did say the 9mhz reference into an Si5351A?
"did indeed degrade various aspects, including phase noise and spectral purity" he also said that was at VHF.? ? And that at very low frequencies it looked fine. Which makes sense. Going from 200mhz to 200khz reduces any phase noise from the 800mhz VCO by a factor of 1000.? How usable an Si5351A with an out-of-spec reference oscillator might be I really don't know. Jerry Anyway someone did more study on it, looking also at 30MHz reference. It did indeed degrade various aspects, including the phase noise and spectral purity. But as I recall, these studies were at VHF output frequencies. I believe when it is operated at the other extreme (LF) there is no significant degradation. Spectral purity is excellent.? |
Some further analysis on high frequency the output of the NEO-7M
The NEO-7M creates its high frequency output by setting the count of the high and the low output in 48MHz ticks. The first divider can thus be minimally be a divide by 2. (one 48MHz tick high and one tick low) and thus the 24MHz output is clean. All other frequencies are created by dynamically adapting the high and low count as in a fractional divider to keep in sync with the requested frequency. If this can be done with a stable high and low count you get little jitter (only the adapting to keep in sync with the GPS) An example is 16MHz with one count high (or low) and 2 counts low (or high) or the 12MHz with 2 high and 2 low If there is not stable high/low count the counts are adapted continuously to get to the required output. And example is 10MHz which is between a divide by 4 and divide by 5 so every couple of output pulses the? pulse is stretched with one 48MHz count to get the divide by 4.8 This suggests that using the 24MHz output as reference for a SI5351 could work but if the XCO of the NEO-7M is a tiny bit high so you get from time to time stretching of the high or low phase output to keep in sync with the GPS. But this pulling will knock the SI5351 PLL out of phase so it always will be very visible in the output of the SI5351 There is no way for the NEO-7M to keep the 24MHz in sync of the XCO is too low. It is clear that the larger the high/low count the cleaner the output of the NEO-7M will be. -- HBTE Files section:?/g/HBTE/files Erik, PD0EK |
Eric,
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Excellent!? ? Thanks for looking into this. Some of the other GPS receivers do give a clean reference clock of perhaps 10mhz.? But not the NEO-7M. Getting back to the Si4432, it seems the best way to lock it to the NEO-7M is through an Si5351, disciplined in firmware to a pules-per-second from the GPS.? ? ? ?/g/HBTE/message/700 ? ?/g/HBTE/message/694 ? Jerry, KE7ER On Mon, Jan 13, 2020 at 02:14 AM, <erik@...> wrote:
Some further analysis on high frequency the output of the NEO-7M |
The NEO-7M output is not great, but PLL's can be surprisingly forgiving. On Mon, Jan 13, 2020 at 02:14 AM, <erik@...> wrote:
Some further analysis on high frequency the output of the NEO-7M |
As the minimum frequency step for the SI4432 is above 100Hz why would you care anyway?
Calibrate from time to time against a known frequency using a calculated compensation and forget about it. But maybe I'm? not ambitious enough -- HBTE Files section:?/g/HBTE/files Erik, PD0EK |
I agree, I'm planning to try a tinySA with a stock Si4432 module once I get the parts in.
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But it's been a fun discussion, I learned a bunch. And accurate frequency standards do have their uses. Jerry, KE7ER On Mon, Jan 13, 2020 at 09:00 AM, <erik@...> wrote: As the minimum frequency step for the SI4432 is above 100Hz why would you care anyway? |
¿ªÔÆÌåÓýWhat about the use of a ¡°jitter cleaner¡± chip whos output clock is equal to
the imput cluck but uses a pll to reduce jitter. Then perhaps the Neo-7M could
drive the jitter cleraner whose output, in turn, drives the SI5351 at 24
MHz?? Here¡¯s an example: https://www.allaboutcircuits.com/technical-articles/clean-clocking-a-new-clock-synthesizer-from-texas-instruments/
-Steve K1RF. ? Sent: Monday, January 13, 2020 11:51 AM
Subject: Re: [HBTE] Using the tinySA to check the NEO-7M GSP locked
output on spurs ?
The NEO-7M output is not great, but PLL's can be surprisingly
forgiving. Some further analysis on high frequency the output of the NEO-7M |
Stability. On Mon, 13 Jan 2020 at 18:00, <erik@...> wrote: As the minimum frequency step for the SI4432 is above 100Hz why would you care anyway? |
Very interesting read indeed, when the parts arrive I will check his post about phase noise measurements to see if he updated the tests with out of spec clock. Here's my source, Hans of QRP-Labs: |
The architecture of that part looks an awful lot like an Si5351.
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A reference clock into a PLL with VCO, the VCO drives three output dividers, just like the Si5351 The article you pointed to states:? ? ? "?jitter is reduced because the input signal passes through the PLL." Could well be that the Si5351 PLL is just as good as a jitter cleaner. Comes down in part to how the low pass filter between the phase detector and the VCO is implemented. I have no idea which part would be better in this regard. Page 23 of the CDCE831 datasheet? ? says;? ? ? Fout = Fin*N/(M*Pdiv)? ? where M=1 to 511, N=1 to 4095, Pdiv=1 to 127 and: Fvco = Fin*N/M? ? must be between 80 and 230 mhz. The 7 to 12 bits in those values severely restricts the possible output frequencies, the (somewhat) corresponding values in the Si5351 fractional dividers are all 20 bits. The Si5351 can hit any target frequency you want in all of HF down to a fraction of a Hz. The Si5351 is a much more aggressive part, costs half as much. Does burn more power though, and the cheap Si5351A part is very restricted in what input (reference) frequencies it is spec'd to work with. Jerry, KE7ER On Mon, Jan 13, 2020 at 06:21 PM, Steven Dick wrote: What about the use of a ¡°jitter cleaner¡± chip whos output clock is equal to the imput cluck but uses a pll to reduce jitter. Then perhaps the Neo-7M could drive the jitter cleraner whose output, in turn, drives the SI5351 at 24 MHz?? Here¡¯s an example: https://www.allaboutcircuits.com/technical-articles/clean-clocking-a-new-clock-synthesizer-from-texas-instruments/ |