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Re: Going digital?
#ubitx
You did not have to use a signal inverter with the easydigi or did you flip it in software? ? ?David |
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Re: uBITX Display Separation Cable
Using old IDE cables is a very good idea.
Note that there are many types of cable available, but most of them will be either 40 wire or 80 wire cables. the difference in the newer (ATA) 80 wire cables is that every other wire is used to separate and shield the signal wires. All 40 ground wires will be connected either to the even side or the odd side of the connector, 2 adjacent wires to each pin. In the older cables, there is no ground wire; each signal is routed through each of the 40 pins. It will work, but provides no shielding. Note also that he signal path in the ATA cables has been cut from 40 to 20 wires. That will make little difference to a lcd connection. The electronic difference is in the interface port. It is a good idea to use the 80 wire cable and determine which side is ground, and then connect that side to ground. That will provide shielding for the signal wires and will cut down on RFI considerably. Note that these connectors have 2 rows of 20 pins each. You will be connecting 16 pins for a 16x2 display. Usually, also, these connectors have a center connector for another drive. Cut the cable so that the shortest of the two connectors are at the ends of it. Note also that the result will usually be a cable with 2 female connectors, so that you will have to make a sort of adapter to provide the normal M-F ends. I don't know if all of this information is exactly correct, but I do know that they work very well. john AD5YE |
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Re: uBITx: Encoder without detents
Those will work, but the 15mm shaft version is even better! Thanks Lucian Mike On Fri, 12 Jan 2018 at 12:16 PM, Lucian Vittori via Groups.Io <lvittori=[email protected]> wrote: Would these work? |
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Re: Going digital?
#ubitx
Hi,
Just to chime in here:? I used the EASY DIGI and a cheapo USB-to-RS232 I bought at the local electronics store.? Wired everything up in the conventional way, tied the EASY DIGI's PTT-HI to the uBITX mic ring, and its PTT-GND to the uBITX mic ground.? Works fine. Not that I didn't have technical difficulties, but they were all on the laptop side.? First, the USB RS232 dongle didn't work until I sacrificed several hours to the driver gods.? It's a good thing I had the presence of mind to unit-test that part with a voltmeter before I did anything else. Next, the laptop failed half the time to detect my audio jack, and the other half the time it sensed the jack but failed to detect any audio.? It turns out that was a simple line-level problem:? if the mic input was too strong, the computer would just assume no valid device was plugged in.? Eventually I learned that I could start the uBITX on the lowest volume level, plug in the audio jack, and raise the volume if necessary; everything would work. Thanks, Xcott K2CAJ |
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Re: Raduino 2.02 VFO A/B mode memory
¿ªÔÆÌåÓýHi Michael
Thanks for the reply. Ok on the next update from Allard. That will be ideal if the mode problem is solved, I will patiently wait until the next release.
Regards Peter G4NJJ
From: [email protected] <[email protected]> on behalf of Michael Babineau <mbabineau.ve3wmb@...>
Sent: 11 January 2018 19:48:27 To: [email protected] Subject: Re: [BITX20] Raduino 2.02 VFO A/B mode memory ?
Peter :?
I believe that Allard will be releasing a V2.0.3 load in the not too distant future. I have been working with him and another list member to Alpha test V2.0.3.? I believe that the issue you are referring to is fixed. I just tried setting up my VFO A with LSB and VFO B with USB I am able to TX on either VFO and switch back and forth without any issues with the mode changing on the VFOs. I am using the V2.0.3 Alpha 2 candidate load. There was a mode switching problem in V2.0.2 that I reported to Allard and he fixed it.? Your current problem may be a side effect of the same issue. Cheers Michael VE3WMB? |
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abc's of the si5351
Now that I got Han's attention, I'll start a new thread.
> Clockbuilderpro seems to do a massive search for the lowest possible integer values of a,b,c in both PLL and output msynth's > when I ask for one output of a particular frequency, often leaving both msynths in fractional mode. Not quite true.? The output MSynth is as reported, low integers but not in integer mode on the few random samples I've tried so far. The PLL MSynth can have fairly large values for B and C, as expected. Jerry? ###################################################### Hans, on a completely different note, you may find this interesting, It takes the three si5351 msynth register values for p1, p2, p3 as reported by Clockbuilderpro and back computes values for a, b, c Just got it to work this morning, seems right but may yet have issues. I assume a,b,c must all be integers. However, a and b could take on fractional values in increments of 1/128 and still yield integer values for p1,p2,p3. I wonder if that's legal, though not seeing that out of Clockbuilderpro. Clockbuilderpro seems to do a massive search for the lowest possible integer values of a,b,c in both PLL and output msynth's when I ask for one output of a particular frequency, often leaving both msynths in fractional mode. So low integer values are likely the primary way to reduce phase noise. This is a considerably different approach than all the C code for the si5351 I find out there on the interwebs Regardless, my guess is that the si5351 has less phase noise in all cases than the typical LC vfo. #include <stdio.h> #include <stdlib.h> int main(int argc, char** argv) { int floorg, floorc, ax128, bx128, a, b, c, p1, p2, p3; if (argc==4) { p1 = atoi(argv[1]); p2 = atoi(argv[2]); p3 = atoi(argv[3]); } else { printf("Usage: Takes 3 int args for si5351 msynth reg values p1,p2,p3\n"); printf("reports int values for a,b,c where a+b/c is the divide ratio\n"); exit(1); } printf(" p1:%d p2:%d p3:%d \n", p1, p2, p3); c = p3; // Given an si5351 msynth divide of (a + b/c): // p1 = 128*a + Floor(128*b/c) - 512 // p2 = 128*b - c*Floor(128*b/c) // p3 = c // All from Silabs AN619 // Since b<c, Floor(128*b/c) has a value between 0 and 127 inclusive // We compute a and b for each of those values, determine which is legal for (floorg=0; floorg<128; floorg++) { // Guess value of Floor(128*b/c) ax128 = p1 + 512 - floorg; // Where ax128 is a*128 bx128 = p2 + c*floorg; // and bx128 is b*128 floorc = bx128/c; // Compute value Floor(128*b/c) a = ax128/128; b=bx128/128; // Report result if value of Floor(128*b/c) is consistent with guess, // and if the computed values for a and b are integers, and b<c. if (floorc==floorg && ax128%128==0 && bx128%128==0 && b<c) printf(" a:%d b:%d c:%d \n", a, b, c); } exit(0); } Jerry, KE7ER |
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Re: AE7EU Top Level PCB Mod
Also, I wonder if a modular design approach could be used, instead of monolithic. Say a better AGC is devised at some point - how to upgrade/replace it? Same question for the filter banks, what about expanding for additional bands? How about injecting a separate DSP module to the audio chain?
Sorry, just thinking out loud. This design is awesome and has made the wheels upstairs start turning -- David K4DBZ Unofficial bitx chatroom:?https://discord.gg/CrHvWFc |
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Re: AE7EU Top Level PCB Mod
Looks pretty awesome!?
Can I recommend using headers for the Teensy?board (as opposed to directly soldering to the board). It adds a little to the cost, but saves headaches down the road when replacing/upgrading the board :)? -- David K4DBZ Unofficial bitx chatroom:?https://discord.gg/CrHvWFc |
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Re: Auto tuner update
You are correct, the LFP caps see half of the peak-to-peak voltage, since that RF is centered on ground.
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In Farhan's example of 3000 ohms at 10W: Vrms*Vrms/Ohms = Watts? ? so? ? Vrms = sqrt(Watts * Ohms) = sqrt(3000*10) = 173.2 Volts RMS across the cap The peak voltage is sqrt(2)=1.414 time the RMS voltage (assuming this is a sine wave halfway through the filter), so 173.2*1.414 = 245 Volts peak to ground. Hans, on a completely different note, you may find this interesting, It takes the three si5351 msynth register values for p1, p2, p3 as reported by Clockbuilderpro and back computes values for a, b, c Just got it to work this morning, seems right but may yet have issues. I assume a,b,c must all be integers. However, a and b could take on fractional values in increments of 1/128 and still yield integer values for p1,p2,p3. I wonder if that's legal, though not seeing that out of Clockbuilderpro. Clockbuilderpro seems to do a massive search for the lowest possible integer values of a,b,c in both PLL and output msynth's when I ask for one output of a particular frequency, often leaving both msynths in fractional mode. So low integer values are likely the primary way to reduce phase noise. This is a considerably different approach than all the C code for the si5351 I find out there on the interwebs Regardless, my guess is that the si5351 has less phase noise in all cases than the typical LC vfo. #include <stdio.h> #include <stdlib.h> int main(int argc, char** argv) { int floorg, floorc, ax128, bx128, a, b, c, p1, p2, p3; if (argc==4) { p1 = atoi(argv[1]); p2 = atoi(argv[2]); p3 = atoi(argv[3]); } else { printf("Usage: Takes 3 int args for si5351 msynth reg values p1,p2,p3\n"); printf("reports int values for a,b,c where a+b/c is the divide ratio\n"); exit(1); } printf(" p1:%d p2:%d p3:%d \n", p1, p2, p3); c = p3; // Given an si5351 msynth divide of (a + b/c): // p1 = 128*a + Floor(128*b/c) - 512 // p2 = 128*b - c*Floor(128*b/c) // p3 = c // All from Silabs AN619 // Since b<c, Floor(128*b/c) has a value between 0 and 127 inclusive // We compute a and b for each of those values, determine which is legal for (floorg=0; floorg<128; floorg++) { // Guess value of Floor(128*b/c) ax128 = p1 + 512 - floorg; // Where ax128 is a*128 bx128 = p2 + c*floorg; // and bx128 is b*128 floorc = bx128/c; // Compute value Floor(128*b/c) a = ax128/128; b=bx128/128; // Report result if value of Floor(128*b/c) is consistent with guess, // and if the computed values for a and b are integers, and b<c. if (floorc==floorg && ax128%128==0 && bx128%128==0 && b<c) printf(" a:%d b:%d c:%d \n", a, b, c); } exit(0); } Jerry, KE7ER On Thu, Jan 11, 2018 at 12:39 pm, Hans Summers wrote:
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Re: Auto tuner update
¿ªÔÆÌåÓýHan's, Thanks for a definitive statement.
A selection of filters and a nice relay switch double sided daughter board would have being nice and I wasn't expecting to be able to use yours for circa 40 watts. I'll plagiarise another design and make do with vero... :-[ Alan On 11/01/2018 19:01, Hans Summers
wrote:
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Bitx40/Raduino bias help
I have a new BitX40 that I am testing on the bench before building it into a case. Right now, it is all stock and I am just testing transmit audio to see how it might be improved. I can receive my signal on a nearby receiver if both are connected to antennas, and hear no distortion or carrier in the signal. In fact, it sounds pretty much like other BitX's I have spoken to on the air with little audio above 1700Hz. However, I cannot hear it at all if it is connected to a dummy load, which led me to measure current draws with the idea I could get an idea of power out with various mic options. I see 0.185amps on receive, and 0.40amp when the PTT is keyed...but it does NOT change when I speak into the mic, no matter how loud I am. I am already past the current draw suggested in the BitX alignment instructions...which I assume must refer to the unit without the Raduino. Should I be playing around with the RV136 in an attempt to see some change when the unit is modulated, or is something else wrong here?
=Vic= |
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Re: Raduino 2.02 VFO A/B mode memory
Peter :?
I believe that Allard will be releasing a V2.0.3 load in the not too distant future. I have been working with him and another list member to Alpha test V2.0.3.? I believe that the issue you are referring to is fixed. I just tried setting up my VFO A with LSB and VFO B with USB I am able to TX on either VFO and switch back and forth without any issues with the mode changing on the VFOs. I am using the V2.0.3 Alpha 2 candidate load. There was a mode switching problem in V2.0.2 that I reported to Allard and he fixed it.? Your current problem may be a side effect of the same issue. Cheers Michael VE3WMB? |
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Re: Micro-BITX ... Lost in post ? Possibly
philip yates
Not long got home, and opened the box.? Now to start the process of working out enclosure sizes, layout etc. Need to get it up and running first tho. Mines F37/1, so an early one in the first batch, looks good. Phil - G7BZD On Thu, Jan 11, 2018 at 7:39 PM, Charlie Morrison <charlie@...> wrote:
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Re: Auto tuner update
The auto tuner capacitors have to be rated for the highest voltage at the highest impedance. This is an extreme requirement. To illustrate, a 10 watt RF signal will put out a peak 30v across a 50 ohms load. However, an end-fed half wave will exhibit about 3000 ohms impedance. At 10 watts, this amounts to a voltahe peak of 250 v. You have to choose the capacitors for 250v rating even for a QRP power level. - f On 12 Jan 2018 12:32 am, "Hans Summers" <hans.summers@...> wrote:
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